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titleCR00140 block diagram


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Main Components

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titleJTAG pins connection

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JTAG Signal

B2B Connector

Pin headerNotes
TMSJ9-55J10-5pull up
TDIJ9-51J10-9pull up
TDOJ9-53J10-3
TCK

J9-59

J10-1pull down
JTAG_EN J9-57-pull up

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


Sensor Interface

The pin headers J1, J2 and J3 constitute the sensor interface. It can be e.g. used with Encoders or Hall sensores. J3 is the selector between differential sensor interface (J2) or single ended sensors (J1). Connecting sensors is only allowed to one of the two pinheaders, the other one has to stay unconnected. In the figure below the jumper configuration of J3  to enable one or the other type of sensor interface is depicted.

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titleCR00140 Jumpers


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The pinheaders are for connection of the sensors are further described in the following table. For differential configuration 100 Ohm parallel termination is used.

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Signal

Pin J1 (singel ended)Pin  J2 (differential)
ISO_ENC_A_P36
ISO_ENC_A_N-5
ISO_ENC_B_P58
ISO_ENC_B_N-7
ISO_ENC_I_P210
ISO_ENC_I_N-9
DGND43
+5.0V_D1, 62


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

CPLD

A Intel/Altera MAX10 FPGA 10M08SAU169C8G is used as system controller. Table below lists the SC CPLD I/O signals and pins:

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Signal nameSC CPLD PinConnected toFunctionNotes





















LEDs

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DesignatorColorConnected toSignal nameActive LevelNote
D1greenU25-B2LED1highUser LED, CPLD Firmware dependent, see Firmware description.
D2greenU25-D6LED0highUser LED, CPLD Firmware dependent, see Firmware description.
D3greenU1-A3, U2-B1PGOODhighON when +15.0V_M and +5.0V_M regulator indicated power good. Connected via transistor T1.
D4greenDC_LINK-lowON when DC_LINK above 11.7V. Connected via comparator U14D to DC_LINK


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DesignatorConnected toSignal nameActive LevelNote
S1U25-B10BUTTON2lowUser button, CPLD Firmware dependent, see Firmware description
S2U25-C10BUTTON1lowUser button, CPLD Firmware dependent, see Firmware description


BEMF

Power and Power-On Sequence

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