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JTAG access to the CPLD of CR00140 is possible via the CRUVI high speed connector J9 or and the pinheader J10, which is a base for TEI004 JTAG programmer. The JTAGEN signal is pulled up and available on J9 only. If JTAGEN is pulled low, the four signals can be used as user I/Os.

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JTAG Signal

B2B Connector

Pin headerNotes
TMSJ9-55J10-5pull up
TDIJ9-51J10-9pull up
TDOJ9-53J10-3-
TCK

J9-59

J10-1pull down
JTAG_EN
JTAGEN J9-57-high for enable JTAG port of CPLD, low for user I/Os, pull up

Sensor Interface

UART_RX-J10-7CPLD Firmware dependent, see Firmware
UART_TX-J10-8CPLD Firmware dependent, see Firmware
RST-J10-6CPLD Firmware dependent, see Firmware
+3.3V_DJ9-4, J9-9J10-4-
DGNDseveral, see CRUVIJ10-2, J10-10-


Sensor Interface

The pin headers J1, J2 and J3 constitute The pin headers J1, J2 and J3 constitute the sensor interface. It can be e.g. used with Encoders or Hall sensoressensors. J3 is the selector between differential sensor interface (J2) or single ended sensors (J1). Connecting sensors is only allowed to one of the two pinheaders (J1/J2), the other one has to stay unconnected. In the figure below the jumper configuration of J3  J3 to enable one or the other type of sensor interface is depicted.

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The pinheaders are for connection of the sensors are further described in the following table. For differential configuration 100 Ohm parallel termination is used.

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Signal

Pin J1
 J1 pin (singel ended)
Pin  J2
 J2 pin (differential)
ISO_ENC_A_P36
ISO_ENC_A_N-5
ISO_ENC_B_P58
ISO_ENC_B_N-7
ISO_ENC_I_P210
ISO_ENC_I_N-9
DGND43
+5.0V_D1, 62

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

CPLD

A Intel/Altera MAX10 FPGA 10M08SAU169C8G is used as system controller. Table below lists the SC CPLD I/O signals and pins:


Motor Interface

CR00140 has a motor interface, where up to 4 phases can be driven.

Warning

Check carefully correct connection of the phases of the motor, according to the motor and the implemented driving algorithm.


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Signal

name
SC CPLD PinConnected toFunctionNotes

LEDs

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 J8 pin lableNote
Motor_AACurrent measurement via R22 and ADC U3
Motor_BBCurrent measurement via R28 and ADC U5
Motor_CC-
Motor_DD-


CRUVI

For the connection to a control unit, the CRUVI interface is implemented. One high speed connector J9 and one low speed connector J11 are assembled. The connectors are further described in section B2B Connectors. The connection of the signals and the voltage levels is described in the CPLD section.

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Signal

 Connector - Pin

X0

J11-3
X1J11-5
X2J11-7

X3

J11-9
X4J11-4
X5J11-10
X6J11-1
X7J11-2
DGND

J11-6,

J9-12, J9-18, J9-24, J9-30, J9-42, J9-48, J9-54, J9-13, J9-19, J9-25, J9-31, J9-37, J9-43, J9-49

+3.3V_D

J11-8, J9-4, J9-9
+5.0V_DJ11-12, J9-60
VADJJ9-36
A0_PJ9-14
A0_NJ9-16
A1_P

J9-20

A1_NJ9-22
A2_PJ9-26
A2_NJ9-28
A3_PJ9-32
A3_NJ9-34
A4_PJ9-38
A4_NJ9-40
A5_PJ9-44
A5_NJ9-46
B0_PJ9-15
B0_NJ9-17
B1_PJ9-21
B1_NJ9-23
B2_PJ9-27
B2_NJ9-29
B3_PJ9-33
B3_NJ9-35
B4_PJ9-398
B4_NJ9-41
B5_PJ9-45
B5_NJ9-47
HSIOJ9-2
HSOJ9-6
RESETJ9-8
HSIJ9-10

TDI

J9-51
TDOJ9-53
TMSJ9-55
JTAGENJ9-57
TCKJ9-59
SMB_ALERTJ9-3
SMB_SDAJ9-5
SMB_SCLJ9-7
REFCLKJ9-11


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs

CPLD

A Intel/Altera MAX10 FPGA 10M08SAU169C8G (U25) is used as system controller. Table below lists the SC CPLD I/O signals and pins.

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Signal nameSC CPLD PinCPLD BankConnected toFunctionNotes

X0

B98J11-3CPLD firmware dependentSee CPLD Firmware
X1A88J11-5CPLD firmware dependentSee CPLD Firmware
X2A78J11-7CPLD firmware dependentSee CPLD Firmware

X3

A68J11-9CPLD firmware dependentSee CPLD Firmware
X4D88J11-4CPLD firmware dependentSee CPLD Firmware
X5B68J11-10CPLD firmware dependentSee CPLD Firmware
X6C98J11-1CPLD firmware dependentSee CPLD Firmware
X7E88J11-2CPLD firmware dependentSee CPLD Firmware
A0_PJ83J9-14CPLD firmware dependentSee CPLD Firmware
A0_NK83J9-16CPLD firmware dependentSee CPLD Firmware
A1_PM133

J9-20

CPLD firmware dependentSee CPLD Firmware
A1_NM123J9-22CPLD firmware dependentSee CPLD Firmware
A2_PM93J9-26CPLD firmware dependentSee CPLD Firmware
A2_NM83J9-28CPLD firmware dependentSee CPLD Firmware
A3_PN83J9-32CPLD firmware dependentSee CPLD Firmware
A3_NN73J9-34CPLD firmware dependentSee CPLD Firmware
A4_PM73J9-38CPLD firmware dependentSee CPLD Firmware
A4_NN63J9-40CPLD firmware dependentSee CPLD Firmware
A5_PK53J9-44CPLD firmware dependentSee CPLD Firmware
A5_NJ53J9-46CPLD firmware dependentSee CPLD Firmware
B0_PN53J9-15CPLD firmware dependentSee CPLD Firmware
B0_NN43J9-17CPLD firmware dependentSee CPLD Firmware
B1_PJ73J9-21CPLD firmware dependentSee CPLD Firmware
B1_NK73J9-23CPLD firmware dependentSee CPLD Firmware
B2_PL113J9-27CPLD firmware dependentSee CPLD Firmware
B2_NM113J9-29CPLD firmware dependentSee CPLD Firmware
B3_PL103J9-33CPLD firmware dependentSee CPLD Firmware
B3_NM103J9-35CPLD firmware dependentSee CPLD Firmware
B4_PJ63J9-398CPLD firmware dependentSee CPLD Firmware
B4_NK63J9-41CPLD firmware dependentSee CPLD Firmware
B5_PL53J9-45CPLD firmware dependentSee CPLD Firmware
B5_NL43J9-47CPLD firmware dependentSee CPLD Firmware
HSION93J9-2CPLD firmware dependentSee CPLD Firmware
HSON103J9-6CPLD firmware dependentSee CPLD Firmware
RESETM53J9-8CPLD firmware dependentSee CPLD Firmware
HSIN123J9-10CPLD firmware dependentSee CPLD Firmware

TDI

F51BJ9-51, J10-9JTAG / user IO CPLD firmware dependentSee CPLD Firmware
TDOF61BJ9-53, J10-3JTAG / user IO CPLD firmware dependentSee CPLD Firmware
TMSG11BJ9-55, J10-5JTAG / user IO CPLD firmware dependentSee CPLD Firmware
JTAGENE51BJ9-57JTAG enable CPLD firmware dependentSee CPLD Firmware
TCKG21BJ9-59, J10-1JTAG / user IO CPLD firmware dependentSee CPLD Firmware
SMB_ALERTK22J9-3CPLD firmware dependentSee CPLD Firmware
SMB_SDAH52J9-5CPLD firmware dependentSee CPLD Firmware
SMB_SCLH42J9-7CPLD firmware dependentSee CPLD Firmware
REFCLKM22J9-11CPLD firmware dependentSee CPLD Firmware
BUTTON1C108S2CPLD firmware dependentactiv low, See CPLD Firmware 
BUTTON2B108S1CPLD firmware dependentactiv low, See CPLD Firmware 
ENC_AA108U13-13Sensor input channel A-
ENC_BA98U13-12Sensor input channel B-
ENC_IA118U13-14Sensor input channel I-
LED0D68D2CPLD firmware dependentSee CPLD Firmware
LED1B28D1CPLD firmware dependentSee CPLD Firmware
M_BEMF_B_DB58U15-13Back EMF signal phase B-
M_BEMF_C_DA58U15-12Back EMF signal phase C-
M_BEMF_A_DA48

U15-14

Back EMF signal phase A-
M_PWM_AHF11AU8-2Phase A half bridge high (DC_LINK) side driver signal-
M_PWM_ALE31AU8-3Phase A half bridge low (PGND) side driver signal-
M_PWM_BHE11AU9-2Phase B half bridge high (DC_LINK)side driver signal-
M_PWM_BLD11AU9-3Phase B half bridge low (PGND) side driver signal-
M_PWM_CHE41AU10-2Phase C half bridge high (DC_LINK)side driver signal-
M_PWM_CLC11AU10-3Phase C half bridge low (PGND) side driver signal-
M_PWM_DHC21AU11-2Phase D half bridge high (DC_LINK) side driver signal-
M_PWM_DLB11AU11-3Phase D half bridge low (PGND) side driver signal-
SD_IAE68U3-6Current measurement phase A33 Ohm series Resistor
SCLK_AB38U3-7, U5-7Clock for ADC for current measurement phase A and B(5-20 MHz)
SD_VB48U7-6Voltage measurement DC_LINK33 Ohm series Resistor
SD_IBA28U5-6Current measurement phase B33 Ohm series Resistor
SCLK_V_AA38U7-7Clock for ADC for voltage measurement DC_LINK(5-20 MHz)
M_DISABLE_D_DJ12U11-5Halfe bridge disable phase Ddisabled when high, pull up connected
M_DISABLE_A_DM12U8-5Halfe bridge disable phase Adisabled when high, pull up connected 
M_DISABLE_B_DL22U9-5Halfe bridge disable phase Bdisabled when high, pull up connected 
M_DISABLE_C_DK12U10-5Halfe bridge disable phase Cdisabled when high, pull up connected 
REFCLKM22J9-11CPLD firmware dependent-
RSTM32J10-6CPLD firmware dependent-
UART_RXN22J10-7CPLD firmware dependent-
UART_TXN32J10-8CPLD firmware dependent-
CLK_25MHZH62U26-3Clock input for accurate 25 Mhz clk.-


CPLD Bank Voltages

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Bank          

Schematic Name

Voltage

Notes
1A+3.3V_D3.3VProvided via CRUVI
1B

+3.3V_D

3.3VProvided via CRUVI
2+3.3V_D3.3VProvided via CRUVI
3VADJ1.8V, 2.5V, 3.3VProvided via CRUVI, supported voltage levels are determined by the CPLD Firmware, and the connected base/controller.
8+3.3V_D3.3V

Provided via CRUVI


LEDs

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DesignatorColorConnected toSignal nameActive LevelNote
D1greenU25-B2LED1highUser LED, CPLD Firmware dependent, see Firmware description.
D2greenU25-D6LED0highUser LED, CPLD Firmware dependent, see Firmware description.
D3greenU1-A3, U2-B1PGOODhighON when +15.0V_M and +5.0V_M regulator indicated power good. Connected via transistor T1.
D4greenDC_LINK-lowON when DC_LINK above 11.7V. Connected via comparator U14D to DC_LINK


Buttons

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DesignatorConnected toSignal nameActive LevelNote
S1U25-B10BUTTON2lowUser button, CPLD Firmware dependent, see Firmware description.
S2U25-C10BUTTON1lowUser button, CPLD Firmware dependent, see Firmware description.


ADCs

There are three isolating AD7403-8 ADCs for continous measurement oft phase A current (U3), phase B current (U5) and the DC_LINK voltage (U7) on board. The currents are measured through the shunt resistors R22, R28 for phase A and B respectively. The ADC clock is routed to the CPLD. For Currents the clock has the signal lable SCLK_A and for the voltage SCLK_V_A. The data signals are also routed to the CPLD. See CPLD Firmware for further description.

BEMF

Back EMF zero crossing signals for sensorless motor control are implemented for Phase A, B and C. They are routed via a triple channel Digital isolator (U15) to the CPLD. See CPLD Firmware for further description.

Half bridge drivers

Four ADuM7223 isolated half bridge drivers (U8, U9, U10, U11) are used for driving the four phases.

DCDCs

There are two DCDCs on board. LTM8053 is utilized for the generation of 15V  U1

DCDC for 5V, U2

two? further isolated are used for the generation of clean for ADC U4, U6

Buttons

...

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titleOn-board LEDs

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Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" Guidline" .


Power Supply

The motor driving stage is supplied via connector J7 with maximum of 40V DC. Polarity of the powersupply is noted on the PCB.  

Warning

Check powersupply for correct polarity. Inversion of polarity will damage the module. At least Transistor T11 may be harmed.

Power

...

Consumption

The power consumption on the motor stage side (J7) is dominated by the connected motor and the corresponding driving algorithm. The idle consumption is given below.

Power supply with minimum current capability of xx A for system startup is recommended.

Power Consumption

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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Distribution
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Power Input PinTypical CurrentNote
VIN~ 47mA @24V (J7), no motor connected, no pwm signal driven.


Power Distribution Dependencies

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Power-On Sequence

There is no power sequence

Voltage Monitor Circuit

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titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

Connectors


DirectionNotes

Bank Voltages

Notes

+3.3V_D

J11-8, J9-4, J9-9In
+5.0V_DJ11-12, J9-60In
VADJJ9-36In
VINJ7Inisolated to the others
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Bank          

Schematic Name

Voltage


Board to Board Connectors

PD: 6 x 6 SoM LSHM B2B Connectors

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  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,series,

    For exampleFor example: 6 x 6 SoM LSHM B2B Connectors

Include Page
PD:6 x 6 SoM LSHM B2B Connectors

? x ? modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

3 x REF-??????? (compatible to ????????), (?? pins, ?? per row)

  • Include Page
    PD:6 x 6 SoM LSHM B2B Connectors
    PD:6 x 6 SoM LSHM B2B Connectors

Include Page
CRUVI B2B Connectors
CRUVI B2B Connectors

...

Technical Specifications

Absolute Maximum Ratings

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SymbolsDescriptionMinMaxUnit
VINMotor supply voltage
42V

+3.3V_D




VV
+5.0V_D


VV
VADJ


V
VVIN


V


Recommended Operating Conditions

...

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ParameterMinMaxUnitsReference Document
VIN
40VSee ???? datasheets.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



VSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.



°CSee Xilinx ???? datasheet.


Physical Dimensions

  • Module size: ?? 68.35 mm × ?? 131 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: ? 5 mm.

PCB thickness: ?? 1.6 mm.

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


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