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Template Revision 2.6 7 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 20182019.32
  • QSPI
  • SDK
  • Custom Carrier (minimum PS Design with available module components only)
  • Modified FSBL (some additional outputs only)
  • Special FSBL for QSPI Programming

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2018-07-112
DateVivadoProject BuiltAuthorsDescription
20192020-0801-092220182019.32TE0808-test_board_noprebuilt-vivado_20182019.32-build_073_2019080913154620200122142231.zip
TE0808-test_board-vivado_20182019.32-build_073_2019080913152220200122142208.zip		John HartfieHartfiel
  • 2019.2 update
  • Vitis support
  • FSBL SI programming procedure update new assembly variants
2019-0508-06092018.3TE0808-test_board_noprebuilt-vivado_2018.3-build_0507_2019050712414120190809131546.zip
TE0808-test_board-vivado_2018.3-build_0507_2019050712413020190809131522.zip		John Hartfiel
  • custom FSBL
  • new assembly variants
2019-05-062018.3TE0808-test_board_noprebuilt-vivado_2018.3-build_05_20190507124141.zip
TE0808-test_board-vivado_2018.3-build_05_20190507124130.zip		John Hartfiel
  • custom FSBL
2018-07-112018.2TE0808-test_board_noprebuilt-vivado_2018.2-build_02_20180711143743.zip
TE0808-test_board-vivado_2018.2-build_02_20180711143702.zip		John Hartfiel
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-03-292017.4TE0808-test_board-vivado_2017.4-build_07_20180329151341.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_07_20180329151355.zip		John Hartfiel
  • new assembly variant
2018-01-162017.4TE0808-test_board-vivado_2017.4-build_04_20180116144644.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_04_20180116144657.zip		John Hartfiel
  • Update Board Part for TEBF0808
    • no changes for test board design and minimal board parts
2018-01-152017.4TE0808-test_board-vivado_2017.4-build_03_20180115084954.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_03_20180115085020.zip		John Hartfiel
  • rework Board Part Files
2017-12-202017.2

TE0808-test_board-vivado_2017.2-build_07_20171220192501.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_07_20171220192448.zip

John Hartfiel
  • Update Board Part Files
2017-11-222017.2TE0808-test_board-vivado_2017.2-build_05_20171122080211.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171122080228.zip		John Hartfiel
  • Update Board Part CSV File
  • Regenerate design
2017-11-162017.2

TE0808-test_board-vivado_2017.2-build_05_20171116151545.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171116151600.zip

John Hartfiel
  • Update Board Part CSV File with new Flash assembly variants
2017-11-132017.2TE0808-test_board-vivado_2017.2-build_05_20171113140954.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171113141908.zip		John Hartfiel
  • initial release


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titleSoftware

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SoftwareVersionNote
VivadoVitis20182019.32needed
SDK2018.3needed

Hardware

, Vivado is included into Vitis installation



Hardware

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Notes :

  • list of software which was used to generate the design

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Slower DDR Speed                     
TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Slower DDR Speed                     
TE0808-04-09EG-1EA  9eg_1e_2gb   REV04       2GB      64MB       NA         NA               
TE0808-04-09EG-1EB  9eg_1e_4gb   REV04       4GB      64MB       NA         NA               
TE0808-04-09EG-1ED  9eg_1e_4gb   REV04       4GB      64MB       NA         1 mm connectors
TE0808-04-09EG-2IB  9eg_2i_4gb   REV04       4GB      64MB       NA         NA               
TE0808-04-15EG-1EB  15eg_1e_4gb  REV04       4GB      64MB       NA         NA               
TE0808-04-09EG-1EE  9eg_1e_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-09EG-1EL  9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-09EG-2IE  9eg_2i_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-15EG-1EE  15eg_1e_4gb  REV04       4GB      128MB      NA         NA               
TE0808-04-06EG-1EE  6eg_1e_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-06EG-1E3  6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-6GI21-L   6eg_2i_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-6GI21-A   6eg_2i_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-6BI21-A   6eg_1i_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-9GI21-A   9eg_2i_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-9BE21-A   9eg_1e_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-6BE21-L   6eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-6BE21-A   6eg_1e_4gb   REV04       4GB      128MB      NA         NA               
TE0808-04-9BE21-L   9eg_1e_4gb   REV04       4GB      128MB      NA         1 mm connectors
TE0808-04-BBE21-A   15eg_1e_4gb  REV04       4GB      128MB      NA         NA               
TE0808-04-6BI21-X6eg_1i_4gbREV04       4GB128MBNANAU41 replaced with schottky diodes


Note: Design contains also Board Part Files for TE0803+TEBF0808 configuration, this boart part files are not used for this reference design.

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib		Vivado Project will be generated by TE Scripts
SDK/HSIVitis<design name>/sw_libAdditional Software Template for SDK/HSI Vitis and apps_list.csv with settings automatically for HSIVitis app generation


Additional Sources

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Notes :

  • prebuilt files
  • Template Table:


    • Scroll Title
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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfxsaExported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems



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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfxsaExported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


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Reference Design is available on:

Design Flow

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Notes :

  • Basic Design Steps

  • Add/ Remove project specific description

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  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. S(optional for manual changes)elect correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
       Important: Use Board Part Files, which did not ends with *_tebf0808
  5. Create HDF XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDKVitis
    1. Run on Vivado TCL: TE::sw_run_hsivitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdkvitis
      Note: See SDK Projects  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis


Launch

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Note:

  • Programming and Startup procedure

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0808
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup

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  1. ) on setup

SD

This does not work, because SD controller is not selected on PS.

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  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select QSPI Card as Boot Mode
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. ZynqMP Boot ROM loads PMU Firmware and  FSBL from QSPI into OCM, 2. FSBL loads Application into DDR

Debugging:

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System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

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Design specific constrain

Not needed.

Software Design -

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Vitis

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Note:

  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:SDK Projects

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 20182019.3 2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 20182019.3 2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 20182019.3 2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)

  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

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General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Template location: ./sw_lib/sw_apps/

zynqmp_fsbl

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

zynqmp_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

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DateDocument Revision

Authors

Description

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infoTypeCurrent version
dateFormatyyyy-MM-dd
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infoTypeModified by
typeFlat

  • new assembly variants
  • Release 2019.2
2019-08-09v.24John Hartfiel
  • new assembly variants
  • small document style update
2019-05-07v.22John Hartfiel
  • Release 2018.3
2018-07-11v.21John Hartfiel
  • Release 2018.2

2018-03-29

v.20John Hartfiel
  • new assembly variant
2018-02-08v.19John Hartfiel
  • Release 2017.4
2017-12-20v.14John Hartfiel
  • Design Update
  • typo correction on documentation
2017-11-22v.10John Hartfiel
  • Update assembly versions with new Flash size
  • Udate HW Table Name
  • Update Design
2017-11-14v.6John Hartfiel
  • Release 2017.2
--all

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infoTypeModified users
dateFormatyyyy-MM-dd
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