Page History

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Template Revision 2.6 7 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Notes :

Add basic key futures, which can be tested with the design

Excerpt
Vitis/Vivado 20182019.32 TEBF0808 Linux USB ETH MAC from EEPROM PCIe SATA SD I2C RGPIO DP user LED access Modified FSBL for Si5338 programming Special FSBL for QSPI Programming

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Date	Vivado	Project Built	Authors	Description
2020-01-23	2019.2	TE0803-StarterKit_noprebuilt-vivado_2019.2-build_3_20200123065955.zip TE0803-StarterKit-vivado_2019.2-build_3_20200123065933.zip	John Hartfiel	2019.2 update Vitis support FSBL SI programming procedure update petalinux device tree and u-boot update
2019-05-07	2018.3	TE0803-StarterKit-vivado_2018.3-build_05_20190507093424.zip TE0803-StarterKit_noprebuilt-vivado_2018.3-build_05_20190507093443.zip	John HartfieHartfiel	new assembly variant TE Script update rework of the FSBLs SI5338 CLKBuilder Pro Project some additional Linux features MAC from EEPROM new assembly variants remove special compiler flags, which was needed in 2018.2
2018-10-25	2018.2	TE0803-Starterkit-vivado_2018.2-build_03_20181026141553.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_03_20181026141611.zip	John Hartfiel	new assembly variant
2018-08-14	2018.2	TE0803-Starterkit-vivado_2018.2-build_02_20180814103204.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180814103221.zip	John Hartfiel	new assembly variant
2018-07-23	2018.2	TE0803-Starterkit-vivado_2018.2-build_02_20180723204618.zip TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180723204638.zip	John Hartfiel	correction on FSBL
2018-07-12	2018.2	TE0803-Starterkit_noprebuilt-vivado_2018.2-build_02_20180713085800.zip TE0803-Starterkit-vivado_2018.2-build_02_20180713085740.zip	John Hartfiel	small petalinux changes IO renaming PL Design changes additional notes for FSBL generated with Win SDK changed *.bif
2018-05-17	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_09_20180517141540.zip TE0803-Starterkit-vivado_2017.4-build_09_20180517141523.zip	John Hartfiel	new assembly variant solved Linux flash issue
2018-04-11	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_07_20180411082139.zip TE0803-Starterkit-vivado_2017.4-build_07_20180411082116.zip	John Hartfiel	bugfix TE0803-01-04EG board part file
2018-02-13	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_06_20180213120642.zip TE0803-Starterkit-vivado_2017.4-build_06_20180213120615.zip	John Hartfiel	new assembly variant
2018-02-06	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180206082527.zip TE0803-Starterkit-vivado_2017.4-build_05_20180206082513.zip	John Hartfiel	same CLK for both VIO
2018-02-05	2017.4	TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180205154248.zip TE0803-Starterkit-vivado_2017.4-build_05_20180205154230.zip	John Hartfiel	new assembly variant solved JTAG/Linux issue
2018-01-31	2017.4	TE0803-Starterkit-vivado_2017.4-build_05_20180131124042.zip TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180131124057.zip	John Hartfiel	new assembly variant
2018-01-18	2017.4	TE0803-Starterkit-vivado_2017.4-build_05_20180118164553.zip TE0803-Starterkit_noprebuilt-vivado_2017.4-build_05_20180118164613.zip	John Hartfiel	initial release

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Software	Version	Note
VivadoVitis	20182019.32	needed
SDK	2018.3	needed
PetaLinux	2018.3	needed
, Vivado is included into Vitis installation
PetaLinux	2019.2	needed
SI SI ClockBuilder Pro	---	optional

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Type	Location	Notes
Vivado	<design name>/block_design <design name>/constraints <design name>/ip_lib	Vivado Project will be generated by TE Scripts
SDK/HSIVitis	<design name>/sw_lib	Additional Software Template for SDK/HSI Vitis and apps_list.csv with settings automatically for HSIVitis app generation
PetaLinux	<design name>/os/petalinux	PetaLinux template with current configuration

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Notes :

prebuilt files

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Debian SD-Image	*.img	Debian Image for SD-Card
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdfxsa	Exported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
MCS-File	*.mcs	Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
MMI-File	*.mmi	File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems
SREC-File	*.srec	Converted Software Application for MicroBlaze Processor Systems

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File	File-Extension	Description
BIF-File	*.bif	File with description to generate Bin-File
BIN-File	*.bin	Flash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File	*.bit	FPGA (PL Part) Configuration File
DebugProbes-File	*.ltx	Definition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports	---	Report files in different formats
Hardware-Platform-Specification-Files	*.hdfxsa	Exported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux
LabTools Project-File	*.lpr	Vivado Labtools Project File
OS-Image	*.ub	Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File	*.elf	Software Application for Zynq or MicroBlaze Processor Systems

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Reference Design is available on:

TE0803 "StarterKit" Reference Design

Design Flow

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Notes :

Basic Design Steps
Add/ Remove project specific description

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_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Press 0 and enter to start "Module Selection Guide"
(optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
Create Project
1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
  Note: Select correct one, see TE Board Part Files
  Important: Use Board Part Files, which ends with *_tebf0808
Create HDF XSA and export to prebuilt folder
1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
  Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
1. HDF XSA is exported to "prebuilt\hardware\<short name>"
  Note: HW Export from Vivado GUI create another path as default workspace.
2. Create Linux images on VM, see PetaLinux KICKstart
  1. Use TE Template from /os/petalinuxNote: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
Generate Programming Files with HSI/SDKVitis
1. Run on Vivado TCL: TE::sw_run_hsivitis -all
  Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdkvitis
  Note: See SDK Projects TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

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Note:

Programming and Startup procedure

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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Get prebuilt boot binaries

_create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
Press 0 and enter to start "Module Selection Guide"
1. Select assembly version
2. Validate selection
3. Select Create and open delivery binary folder
  Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Optional for Boot.bin on QSPI Flash and image.ub on SD.

Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible

Copy image.ub on SD-Card

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1. use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
2. or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
Set Boot Mode to QSPI-Boot and insered SD.
1. Depends on Carrier, see carrier TRM.
2. TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area

SD

Copy image.ub and Boot.bin on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
Insert SD-Card in SD-Slot.

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title	Vivado Hardware Manager

System Design - Vivado

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Description of Block Design,

HTML

<!-- Description of Block Design,

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Block Design

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title	Block Design

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Code Block

language	ruby
title	_i_io.xdc

# system controller ip
#LED_HD SC0 J3:31
#LED_XMOD SC17 J3:48 
#CAN RX SC19 J3:52 B26_L11_P
#CAN TX SC18 J3:50 B26_L11_N
#CAN S  SC16 J3:46 B26_L1_N

set_property PACKAGE_PIN G14 [get_ports BASE_sc0]
set_property PACKAGE_PIN D15 [get_ports BASE_sc5]
set_property PACKAGE_PIN H13 [get_ports BASE_sc6]
set_property PACKAGE_PIN H14 [get_ports BASE_sc7]
set_property PACKAGE_PIN A13 [get_ports BASE_sc10_io]
set_property PACKAGE_PIN B13 [get_ports BASE_sc11]
set_property PACKAGE_PIN A14 [get_ports BASE_sc12]
set_property PACKAGE_PIN B14 [get_ports BASE_sc13]
set_property PACKAGE_PIN F13 [get_ports BASE_sc14]
set_property PACKAGE_PIN G13 [get_ports BASE_sc15]
set_property PACKAGE_PIN A15 [get_ports BASE_sc16]
set_property PACKAGE_PIN B15 [get_ports BASE_sc17]
set_property PACKAGE_PIN J14 [get_ports BASE_sc18]
set_property PACKAGE_PIN K14 [get_ports BASE_sc19 ]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]

# Audio Codec
#LRCLK          J3:49 
#BCLK            J3:51 
#DAC_SDATA    J3:53 
#ADC_SDATA    J3:55 
set_property PACKAGE_PIN L13 [get_ports LRCLK ]
set_property PACKAGE_PIN L14 [get_ports BCLK ]
set_property PACKAGE_PIN E15 [get_ports DAC_SDATA ]
set_property PACKAGE_PIN F15 [get_ports ADC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports BCLK ]
set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ]
set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]

Software Design -

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Vitis

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Note:

optional chapter separate
sections for different apps

For SDK project creation, follow instructions from:SDK Projects

Vitis

Application

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----------------------------------------------------------

FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 20182019.3 2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

Modified Files: blconfig.h, bootloader.c
Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 20182019.3 2 xilisf_v5_11

Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

zynq_fsbl

TE modified 20182019.3 2 FSBL

General:

Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device ID

Module Specific:

Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY

zynq_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

Modified Files: main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 20182019.3 2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

Module Specific:

Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

SDK template in ./sw_lib/sw_apps/ available.

zynqmp_fsbl

TE modified 20182019.3 2 FSBL

General:

Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
General Changes:
- Display FSBL Banner and Device Name

...

zynqmp_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation

...

Start with petalinux-config -c u-boot
Changes:

CONFIG_ENV_IS_NOWHERE=y
# CONFIG_ENV_IS_IN_SPI_FLASH is not set

Change platform-top.h:

Code Block

language	js

#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000

#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0" \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO_MMC \
        "dfu_mmc_info=" \
        "set dfu_alt_info " \
        "${kernel_image} fat 0 1\\\\;" \
        "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"

/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#define CONFIG_ZYNQMP_EEPROM
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS          0
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x50
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0xFA
#endif

Device Tree

CONFIG_I2C_EEPROM=y
CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
CONFIG_SYS_I2C_EEPROM_ADDR=0x50
CONFIG_SYS_I2C_EEPROM_BUS=2
CONFIG_SYS_EEPROM_SIZE=256
CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

Change platform-top.h:

Code Block

language	js

Device Tree

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
  chosen {
    xlnx,eeprom = &eeprom;
  };
};

/* notes:
serdes: // PHY TYP see: dt-bindings/phy/phy.h
*/

/* default */

/* SD */

&sdhci1 {
	// disable-wp;
	no-1-8-v;

Code Block

language	js

/include/ "system-conf.dtsi"
/ {
};
/* notes:
serdes: // PHY TYP see: dt-bindings/phy/phy.h
*/

/* default */

/* SD */

&sdhci1 {
	// disable-wp;
	no-1-8-v;

};

/*PCIE*/
&pcie {
     phys = <&lane0 2 0 2 100000000>;  //not recognized at the moment on linux
};

/* DP */ 
&zynqmp_dpsub {
    phys = <&lane3 5 0 3 27000000>; //Xilinx default is 5 (UFS), 6 (DP) does not work
};

/* SATA */

&sata {
    //phys = <&lane2 1 0 1 150000000>;  //TE0808,TE0807
    phys = <&lane2 1 0 0 150000000>; //TE0803
};


/* USB  */


&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    snps,usb3_lpm_capable;
    snps,dis_u3_susphy_quirk;
    snps,dis_u2_susphy_quirk;
    phy-names = "usb2-phy","usb3-phy";
    phys = <&lane1 4 0 2 100000000>;
    maximum-speed = "super-speed";
};

/* ETH PHY */

&gem3 {
	phy-handle = <&phy0>;
	phy0: phy0@1 {
		device_type = "ethernet-phy";
		reg = <1>;
	};
};

/* QSPI */

&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* I2C */

&i2c0 {
    i2cswitch@73 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x73>;
        i2c-mux-idle-disconnect;
        i2c@0 { // MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled
   compatible = "nxp,pca9548";
        #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x73><0>;
        i2c-mux-idle-disconnect};

        i2c@2i2c@1 { // SFP TEBF0808 PCIePCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2><1>;
        };
        i2c@3i2c@2 { // i2c SFPPCIe
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3><2>;
        };
        i2c@4i2c@3 { // i2cSFP1 SFPTEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4><3>;
        };
        i2c@5i2c@4 { // i2cSFP2 EEPROMTEBF0808
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5><4>;
        };
        i2c@6i2c@5 { // i2cTEBF0808 FMCEEPROM
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;

            si570_2: clock-generator3@5d {
         reg = <5>;
        #clock-cells = <0>;
  eeprom: eeprom@50 {
	            compatible = "silabsatmel,si57024c08";
	            reg = <0x50>;
	        reg = <0x5d>};
        };
        temperature-stabilityi2c@6 = <50>;
  { // TEBF0808 FMC  
            factory#address-foutcells = <156250000><1>;
                clock-frequency#size-cells = <78800000><0>;
            reg }= <6>;
        };
        i2c@7 { // i2cTEBF0808 USB HUB
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
    i2cswitch@77 { // u
        compatible = "nxp,pca9548";
        #address-cells = <1>;
        #size-cells = <0>;
        reg = <0x77>;
        i2c-mux-idle-disconnect;
        i2c@0 { // i2cTEBF0808 PMOD P1
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0>;
        };
        i2c@1 { // i2c Audio Codec
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <1>;
			/*
            adau1761: adau1761@38 {
                compatible = "adi,adau1761";
                reg = <0x38>;
            };
			*/
        };
        i2c@2 { // i2cTEBF0808 FireFlyFirefly A
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <2>;
        };
        i2c@3 { // i2cTEBF0808 FireFlyFirefly B
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <3>;
        };
        i2c@4 { //Module PLL Si5338 i2cor PLLSI5345
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <4>;
        };
        i2c@5 { //TEBF0808 i2c SCCPLD
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <5>;
        };
        i2c@6 { //TEBF0808 i2cFirefly PCF8574DWR
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <6>;
        };
        i2c@7 { // i2cTEBF0808 PMOD P3
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <7>;
        };
    };
};

Kernel

Start with petalinux-config -c kernel

...

CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)
CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set (only needed to fix JTAG Debug issue)CONFIG_EDAC_CORTEX_ARM64=y

Rootfs

Start with petalinux-config -c rootfs

Changes:

CONFIG_i2c-tools=y
CONFIG_busybox-httpd=y (for web server app)
CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

Applications

startup

...

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

startup

Script App to load init.sh from SD Card if available.

webfwu

Webserver application accemble for Zynq access. Need busybox-httpd

...

Scroll Title

anchor	Table_dch
title	Document change history.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths	2,,3,4
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date

Document Revision

Authors

Description

Page info

	modified-date
	modified-date
dateFormat	yyyy-MM-dd

Page info

infoType	Current version
prefix	v.
type	Flat

Page info

	modified-user
	modified-user

Release 2019.2

2019-05-07

v.24

John Hartfiel

Release 2018.3

2018-10-26

v.21

John Hartfiel

new assembly variant

2018-08-14

v.19

John Hartfiel

design update

2018-07-23

v.18

John Hartfiel

new assembly variant

2018-07-20

v.16

John Hartfiel

Release 2018.2

2018-05-17

v.14

John Hartfiel

new assembly variant
solved known issues

2018-04-30

v.13

John Hartfiel

Update known Issues

2018-04-11

v.12

John Hartfiel

bugfix board part files

2018-02-13

v.11

John Hartfiel

new assembly variant
solved known issues

2018-01-29

v.4

John Hartfiel

Update known Issues

2018-01-18

v.3

John Hartfiel

Release 2017.4

All

Page info

	modified-users
	modified-users

...

Trenz Electronic Documentation

Versions Compared

Old Version 24

New Version 25

Key

Design Flow

Launch

QSPI

Get prebuilt boot binaries

QSPI

SD

System Design - Vivado

Block Design

Software Design -

Vitis

Application

scu

srec_spi_bootloader

xilisf_v5_11

zynq_fsbl

zynq_fsbl_flash

zynqmp_fsbl

zynqmp_fsbl_flash

zynqmp_pmufw

hello_te0820

u-boot

zynqmp_fsbl

zynqmp_fsbl_flash

Device Tree

Device Tree

Kernel

Rootfs

Applications

startup

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

startup

webfwu