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Template Revision 2.6 7 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Hardware
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Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.
Design supports following carriers:
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anchor | Table_HWC |
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title | Hardware Carrier |
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Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.
Design supports following carriers:
Additional HW Requirements:
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anchor | Table_AHW |
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title | Additional Hardware |
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For general structure and of the reference design, see Project Delivery - Xilinx devices
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Additional HW Requirements:
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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| Prebuilt files
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BIF-File | *.bif | File with description to generate Bin-File | |||||||||||||||||||
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | |||||||||||||||||||
BIT-File | *.bit | FPGA (PL Part) Configuration File | |||||||||||||||||||
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | |||||||||||||||||||
Debian SD-Image | *.img | Debian Image for SD-Card | |||||||||||||||||||
Diverse Reports | --- | Report files in different formats | |||||||||||||||||||
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | |||||||||||||||||||
LabTools Project-File | *.lpr | Vivado Labtools Project File | |||||||||||||||||||
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | |||||||||||||||||||
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | |||||||||||||||||||
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | |||||||||||||||||||
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | |||||||||||||||||||
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
Additional Sources
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Prebuilt
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orientation | portrait | |||||||||||||||||||||||||||||||||||||||||||||||||||||
sortDirection | ASC | |||||||||||||||||||||||||||||||||||||||||||||||||||||
repeatTableHeaders | default | style | widths | |||||||||||||||||||||||||||||||||||||||||||||||||||
sortByColumn | 1 | |||||||||||||||||||||||||||||||||||||||||||||||||||||
sortEnabled | false | |||||||||||||||||||||||||||||||||||||||||||||||||||||
cellHighlighting | true | |||||||||||||||||||||||||||||||||||||||||||||||||||||
File | File-Extension | Description | ||||||||||||||||||||||||||||||||||||||||||||||||||||
BIF-File | *.bif | File with description to generate Bin-File | ||||||||||||||||||||||||||||||||||||||||||||||||||||
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | ||||||||||||||||||||||||||||||||||||||||||||||||||||
BIT-File | *.bit | FPGA (PL Part) Configuration File | ||||||||||||||||||||||||||||||||||||||||||||||||||||
Diverse Reports | --- | Report files in different formats | ||||||||||||||||||||||||||||||||||||||||||||||||||||
Hardware-Platform-Specification-Files | *.hdf | Exported Vivado Hardware Specification for SDK/HSI and PetaLinux | ||||||||||||||||||||||||||||||||||||||||||||||||||||
LabTools Project-File | *.lpr | Vivado Labtools Project File |
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Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Notes :
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- S(optional for manual changes)elect correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which did not ends with *_tebf0808
- S(optional for manual changes)elect correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
Launch
Programming
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Note:
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0807
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
Use SDK instead of Vivado is also possible, see: SDK Projects#Xilinx%22HelloWorld%22onZynqMP
SD
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with SDK Debugger into device, see:
Usage
QSPI Boot:
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR
Debugging:
System Design - Vivado
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Block Design
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PS Interfaces
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Activated interfaces:
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anchor | Table_PSI |
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title | PS Interfaces |
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Notes :
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
Important: Use Board Part Files, which did not ends with *_tebf0808
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create XAS and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Launch
Programming
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Note:
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Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp hello_te0807
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
SD
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with Vitis Debugger into device.
Usage
QSPI Boot:
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select QSPI Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. ZynqMP Boot ROM loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR
System Design - Vivado
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PS Interfaces
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL. |
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design] set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Not needed.
Software Design - SDK/HSI
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For SDK project creation, follow instructions from:
Application
_design] |
Design specific constrain
Not needed.
Software Design - SDK/HSI
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For SDK project creation, follow instructions from:
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin. |
Template location: ./sw_lib/sw_apps/
zynqmp_fsbl
TE modified 20182019.3 2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
zynqmp_fsbl_flash
TE modified 20182019.3 2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
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2019-05-22 | v.10 | John Hartfiel |
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2019-02-07 | v.9 | John Hartfiel |
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2018-09-04 | v.7 | John Hartfiel |
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2018-02-08 | v.5 | John Hartfiel |
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2017-11-14 | v.3 | John Hartfiel |
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-- | all |
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