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Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

Design supports following carriers:

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Note: Design contains also Board Part Files for TE0807 only configuration, this boart part files are not used for this reference design.

Design supports following carriers:

Additional HW Requirements:

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Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional Sources

Additional HW Requirements:

Prebuilt

Content

For general structure and of the reference design, see Project Delivery - Xilinx devices

Design Sources

Additional Sources

Prebuilt

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0807 "StarterKit" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Removed
2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
5. Create Project
   
   1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which ends with *_tebf0808
6. Create HDF and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
7. Create Linux (bl31.elf, uboot.elf and image.ub) with exported HDF
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
         Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
8. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
   
   1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
9. Generate Programming Files with HSI/SDK
   
   1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

Reference Design is available on:

• TE0807 "StarterKit" Reference Design

Design Flow

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

• Xilinx Development Tools
• Vivado Projects - TE Reference Design
• Project Delivery.

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
   Image Added
2. Press 0 and enter to start "Module Selection Guide"
3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
   
   1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
                Important: Use Board Part Files, which ends with *_tebf0808
5. Create XSA and export to prebuilt folder
   
   1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
6. Create Linux (bl31.elf, uboot.elf and image.ub) with exported XSA
   
   1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
   2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
7. Add Linux files (bl31.elf, uboot.elf and image.ub) to prebuilt folder
   
   1. prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
8. Generate Programming Files with Vitis
   
   1. Run on Vivado TCL: TE::sw_run_vitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
   2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis

Launch

For For basic board setup, LEDs... see: TEBF0808 Getting Started

...

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Get prebuilt boot binaries

1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
2. Press 0 and enter to start "Module Selection Guide"
   1. Select assembly version
   2. Validate selection
   3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin Optional for Boot.bin on QSPI Flash and image.ub on SD.

1. Connect JTAG and power on carrier with module
2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
   Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
            optional "TE::pr_program_flash_binfile -swapp hello_te0803" possible
4. Copy image.ub on SD-Card

   ...

   1. 1. use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
      2. or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
   2. Set Boot Mode to QSPI-Boot and insered SD.
      1. Depends on Carrier, see carrier TRM.
      2. TEBF0808 change automatically the Boot Mode to SD, if SD is insered, optional CPLD Firmware without Boot Mode changing for mircoSD Slot is available on the download area

   SD

   1. Copy image.ub and Boot.bin on SD-Card.
      • use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
      • or use
      • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
   2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
   3. Insert SD-Card in SD-Slot.

   ...

   Scroll Title
   anchor Figure_VHM title Vivado Hardware Manager

   System Design - Vivado

   Page properties
   hidden true id Comments
   Note: Description of Block Design,
   HTML
   <!-- Description of Block Design, Constrains... BD Pictures from Export...   -->

   Block Design

   Scroll Title
   anchor Figure_BD title Block Design

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   Code Block
   language ruby title _i_io.xdc
   #System Controller IP #J3:31 LED_HD set_property PACKAGE_PIN K11 [get_ports BASE_sc0] #J3:41 set_property PACKAGE_PIN E14 [get_ports BASE_sc5] #J3:45 set_property PACKAGE_PIN C12 [get_ports BASE_sc6] #J3:47 set_property PACKAGE_PIN D12 [get_ports BASE_sc7] #J3:32 set_property PACKAGE_PIN J12 [get_ports BASE_sc10_io] #J3:34 set_property PACKAGE_PIN K13 [get_ports BASE_sc11] #J3:36 set_property PACKAGE_PIN A13 [get_ports BASE_sc12] #J3:38 set_property PACKAGE_PIN A14 [get_ports BASE_sc13] #J3:40 set_property PACKAGE_PIN E12 [get_ports BASE_sc14] #J3:42 set_property PACKAGE_PIN F12 [get_ports BASE_sc15] #J3:46 CAN S set_property PACKAGE_PIN A12 [get_ports BASE_sc16] #J3:48 LED_XMOD set_property PACKAGE_PIN B12 [get_ports BASE_sc17] #J3:50 CAN TX set_property PACKAGE_PIN B14 [get_ports BASE_sc18] #J3:52 CAN RX set_property PACKAGE_PIN C14 [get_ports BASE_sc19] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18] set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19] # PLL #J4:74 #set_property PACKAGE_PIN AF15 [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_p[0]}] #set_property IOSTANDARD LVDS [get_ports {si570_clk_n[0]}] # Audio Codec #LRCLK J3:49 B47_L9_N #BCLK J3:51 B47_L9_P #DAC_SDATA J3:53 B47_L7_N #ADC_SDATA J3:55 B47_L7_P set_property PACKAGE_PIN G14 [get_ports LRCLK ] set_property PACKAGE_PIN H14 [get_ports BCLK ] set_property PACKAGE_PIN C13 [get_ports DAC_SDATA ] set_property PACKAGE_PIN D14 [get_ports ADC_SDATA ] set_property IOSTANDARD LVCMOS18 [get_ports LRCLK ] set_property IOSTANDARD LVCMOS18 [get_ports BCLK ] set_property IOSTANDARD LVCMOS18 [get_ports DAC_SDATA ] set_property IOSTANDARD LVCMOS18 [get_ports ADC_SDATA ]

   Software Design -

   ...

   Vitis

   Page properties
   hidden true id Comments
   Note: optional chapter separate sections for different apps

   For SDK project creation, follow instructions from:SDK Projects

   Vitis

   Application

   Page properties
   hidden true id Comments
   ---------------------------------------------------------- FPGA Example scu MCS Firmware to configure SI5338 and Reset System. srec_spi_bootloader TE modified 20182019.3 2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: Modified Files: blconfig.h, bootloader.c Changes: Add some console outputs and changed bootloader read address. Add bugfix for 2018.2 qspi flash xilisf_v5_11 TE modified 20182019.3 2 xilisf_v5_11 Changed default Flash type to 5. ---------------------------------------------------------- Zynq Example: zynq_fsbl TE modified 20182019.3 2 FSBL General: Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code) Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\ General Changes:  Display FSBL Banner and Device ID Module Specific: Add Files: all TE Files start with te_* READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h) CPLD access Read CPLD Firmware and SoC Type Configure Marvell PHY zynq_fsbl_flash TE modified 20182019.3 2 FSBL General: Modified Files: main.c General Changes:  Display FSBL Banner Set FSBL Boot Mode to JTAG Disable Memory initialisation ZynqMP Example: ---------------------------------------------------------- zynqmp_fsbl TE modified 20182019.3 2 FSBL General: Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code) Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\ General Changes:  Display FSBL Banner and Device Name Module Specific: Add Files: all TE Files start with te_* Si5338 Configuration ETH+OTG Reset over MIO zynqmp_fsbl_flash TE modified 20182019.3 2 FSBL General: Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c General Changes:  Display FSBL Banner Set FSBL Boot Mode to JTAG Disable Memory initialisation zynqmp_pmufw Xilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820 Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-boot U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

   SDK template in ./sw_lib/sw_apps/ available.

   zynqmp_fsbl

   TE modified 20182019.3 2 FSBL

   General:

   • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
   • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
   • General Changes: 
     
     • Display FSBL Banner and Device Name

   ...

   zynqmp_fsbl_flash

   TE modified 20182019.3 2 FSBL

   General:

   • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
   • General Changes:
     
     •  Display FSBL Banner
     • Set FSBL Boot Mode to JTAG
     • Disable Memory initialisation

   ...

   Start with petalinux-config -c u-boot

   Changes:

   • CONFIG_ENV_IS_NOWHERE=y

   • # CONFIG_ENV_IS_IN_SPI_FLASH is not set

   Change platform-top.h:

   ...

   language	js

   ...

   • CONFIG_I2C_EEPROM=y

   • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

   • CONFIG_SYS_

   ...

   • I2C_EEPROM_ADDR=0x50

   • CONFIG_SYS_I2C_EEPROM_BUS=2

   • CONFIG_SYS_EEPROM_SIZE=256

   • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

   • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

   • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

   • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

   Change platform-top.h:

   Code Block
   language js

   Device Tree

   Code Block
   language js
   /include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; }; /* notes: serdes: // PHY TYP see: dt-bindings/phy/phy.h */ /* default */ /* SD */ &sdhci1 { // disable-wp; no-1-8-v;

   Device Tree

   Code Block
   language js
   /include/ "system-conf.dtsi" / { }; /* notes: serdes: // PHY TYP see: dt-bindings/phy/phy.h */ /* default */ /* SD */ &sdhci1 { // disable-wp; no-1-8-v; }; /*PCIE*/ &pcie { phys = <&lane0 2 0 2 100000000>; //not recognized at the moment on linux }; /* DP */ &zynqmp_dpsub { phys = <&lane3 5 0 3 27000000>; //Xilinx default is 5 (UFS), 6 (DP) does not work }; /* SATA */ &sata { phys = <&lane2 1 0 1 150000000>; //TE0808,TE0807 //phys = <&lane2 1 0 0 150000000>; //TE0803 }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; snps,usb3_lpm_capable; snps,dis_u3_susphy_quirk; snps,dis_u2_susphy_quirk; phy-names = "usb2-phy","usb3-phy"; phys = <&lane1 4 0 2 100000000>; maximum-speed = "super-speed"; }; /* ETH PHY */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; <1>; #size-cells = <0><1>; status = "okay"; }; }; /* I2C */ &i2c0 { flash0: flash@0i2cswitch@73 { // u compatible = "jedecnxp,spi-norpca9548"; reg#address-cells = <0x0><1>; #address#size-cells = <1><0>; #size-cellsreg = <1><0x73>; } i2c-mux-idle-disconnect; }; /* I2C */ &i2c0 { i2cswitch@73i2c@0 { // u MCLK TEBF0808 SI5338A, 570FBB000290DG_unassembled compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x73><0>; i2c-mux-idle-disconnect; }; i2c@2i2c@1 { // PCIeSFP TEBF0808 PCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <2><1>; }; i2c@3i2c@2 { // i2c SFPPCIe #address-cells = <1>; #size-cells = <0>; reg = <3><2>; }; i2c@4i2c@3 { // i2cSFP1 SFPTEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <4><3>; }; i2c@5i2c@4 { // i2cSFP2 EEPROMTEBF0808 #address-cells = <1>; #size-cells = <0>; reg = <5><4>; }; i2c@6i2c@5 { // i2cTEBF0808 FMCEEPROM #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_2: clock-generator3@5d { <5>; #clock-cells = <0>; eeprom: eeprom@50 { compatible = "silabsatmel,si57024c08"; reg = <0x50>; reg = <0x5d>}; }; temperature-stabilityi2c@6 = <50>; { // TEBF0808 FMC factory#address-foutcells = <156250000><1>; clock-frequency#size-cells = <78800000><0>; }reg = <6>; }; i2c@7 { // i2cTEBF0808 USB HUB #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; i2cswitch@77 { // u compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // i2cTEBF0808 PMOD P1 #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // i2c Audio Codec #address-cells = <1>; #size-cells = <0>; reg = <1>; /* adau1761: adau1761@38 { compatible = "adi,adau1761"; reg = <0x38>; }; */ }; i2c@2 { // i2cTEBF0808 FireFlyFirefly A #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // i2cTEBF0808 FireFlyFirefly B #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { //Module i2c PLLPLL Si5338 or SI5345 #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { //TEBF0808 i2c SCCPLD #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { //TEBF0808 Firefly i2cPCF8574DWR #address-cells = <1>; #size-cells = <0>; reg = <6>; }; i2c@7 { // i2cTEBF0808 PMOD P3 #address-cells = <1>; #size-cells = <0>; reg = <7>; }; }; };

   Kernel

   Start with petalinux-config -c kernel

   ...

   • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

   • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

   • CONFIG_CPU_FREQ_DEFAULT_GOV_USERSPACE is not set (only needed to fix JTAG Debug issue)CONFIG_EDAC_CORTEX_ARM64=y

   Rootfs

   Start with petalinux-config -c rootfs

   Changes:

   • CONFIG_i2c-tools=y
   • CONFIG_busybox-httpd=y (for web server app)
   • CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

   Applications

   startup

   ...

   See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

   startup

   Script App to load init.sh from SD Card if available.

   webfwu

   Webserver application accemble for Zynq access. Need busybox-httpd

   ...

   Scroll Title
   anchor Table_dch title Document change history.
   Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths 2*,*,3*,4* sortByColumn 1 sortEnabled false cellHighlighting true Date Document Revision Authors Description Page info modified-date modified-date dateFormat yyyy-MM-dd Page info infoType Current version prefix v. type Flat Page info modified-user modified-user new assembly variants Release 2019.2 29-05-22 v.16 John Hartfiel Release 2018.3 2019-09-04 v.13 John Hartfiel Release 2018.2 2018-07-20 v.12 John Hartfiel Design update 2018-04-30 v.10 John Hartfiel Update known issues 2018-02-08 v.9 John Hartfiel Design update 2018-01-29 v.4 John Hartfiel Update known issues 2018-01-18 v.3 John Hartfiel Release 2017.4 All Page info modified-users modified-users

   ...