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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0006 block diagram |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| fitWindow | false |
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| diagramName | TEI0006_OV_BD |
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| simpleViewer | false |
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| links | auto |
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| tbstyle | hidden |
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| lbox | true |
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| diagramWidth | 638639 |
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| revision | 2324 |
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| Scroll Only |
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Main Components
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| Scroll Title |
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| anchor | Figure_OV_BD |
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| title | TEI0006 main components |
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| Scroll Ignore |
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| draw.io Diagram |
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| border | false |
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| viewerToolbar | true |
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| |
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| fitWindow | false |
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| diagramName | TEI0006_OV_MC |
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| simpleViewer | false |
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| links | auto |
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| tbstyle | hidden |
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| lbox | true |
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| diagramWidth | 641 |
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| revision | 68 |
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| Scroll Only |
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- Intel® MAX 10, U18
- DC/DC convertor, U4...11
- SDRAM DDR3 Memory, U12 - U13
- User LEDs, D1...4
- Ethernet Transceiver, U2
- SPI Flash Memory, U1 - U3
- Intel® Cyclone 10 GX, U23
- EEPROM, U64
- Buffer, U16
- 10-Channel Clock Multiplier, U14
- CryptoAuthentication Device (optional), U19
Initial Delivery State
| Page properties |
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Notes : Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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| Scroll Title |
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| anchor | Table_OV_IDS |
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| title | Initial delivery state of programmable devices on the module |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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Storage device name | Content | Notes |
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| Intel® MAX 10 | Programmed | See CPLD Firmware | Quad SPI Flash | Not Programmed |
| | EEPROM | Programmed | Ethernet MAC | | DDR3 SDRAM | Not Programmed |
|
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| Scroll Title |
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| anchor | Table_SIP_B2B |
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| title | General PL I/O to B2B connectors information |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
| FPGA | FPGA Bank | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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Intel Cyclone 10 GX | Bank 1C | J3 | 24 Single ended (12 Diff pair) | 0.95V | GXBL1C_RX0...5 N/P, GXBL1C_TX0...5 N/P | Bank 1D | J3 | 24 Single ended (12 Diff pair) | 0.95V | GXBL1D_RX0...5 N/P, GXBL1D_TX0...5 N/P | Bank 2A | J2 | 2 Single ended | 1.8V | PERST, CLKUSR | Bank 2J | J2 | 46 Single ended (23 Diff pair) | VCCIO2J |
| Bank 2K | J1 | 46 Single ended (23 Diff pair) | VCCIO2K |
| Bank 2L | J1 | 48 Single ended (24 Diff pair) | VADJ up to 3 V |
| Bank 3A | - | - | 1.35V | VDD_DDR | Bank 3B | - | - | 1.35V | VDD_DDR | Intel Max 10 | Bank 1A | J2 | 8 Single ended | 3.3V |
| Bank 1B | J2 | 5 Single ended | 3.3V |
| Bank 2 | J3 | 2 1 Single ended | 1.8VIO |
| Bank 3 | - | - | 1.8VIO |
| Bank 5 | J2 | 4 3 Single ended | 3.3V |
| Bank 6 | J2 | 2 Single ended | 3.3V |
| Bank 8 | J2 | 24 23 Single ended | 3.3V |
|
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JTAG Interface
JTAG access to the TEI0006 SoM is through B2B connector J2. JTAGEN is pulled up to 3.3V and after power on, JTAG will be enabled.for MAX 10 CPLD is enabled. JTAG port of Cyclon 10 GX device is routed to MAX10 CPLD IOs. The default Firmware connects the JTAG port of the Cyclon 10 GX to the IO pins of the JTAG port in user IO mode. Setting JTAGEN to GND enables JTAG for the Cyclon 10 GX device.
| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Title |
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| anchor | Table_SIP_JTG |
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| title | JTAG pins connection |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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JTAG Signal | B2B Connector | Note |
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| TMS | J2-160 |
| | TDI | J2-159 |
| | TDO | J2-158 |
| | TCK | J2-157 |
| | JTAGEN | J2-105 | Pulled up to 3.3V. |
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| Scroll Title |
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| anchor | Table_OBP_MIOs |
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| title | MIOs pins |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| MIO Pin | Connected to | B2B | Notes |
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| MAX_IO1...20, 22 | U18 (Intel MAX 10) - Bank 8 | J2 |
| | MAX_IO23..., 25, 26 | U18 (Intel MAX 10) - Bank 5
| J2 |
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| Scroll Title |
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| anchor | Table_OBP |
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| title | On board peripherals |
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|
| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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|
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QSPI Flash Memory
| Page properties |
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
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Clock Sources
The TEI0006 has three crystal oscillator one crystal, three MEMS oscillators and a programmable clock generator.
| Scroll Title |
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| anchor | Table_OBP_CLK |
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| title | Osillators |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Designator | Description | Frequency |
|---|
NoteCrystal | MEMS Oscillator | 25MHz | U2 Ethernet | | U15 |
Crystal | MEMS Oscillator | 25MHz | IN0 of U14 | | U17 |
Crystal 48MHz | | 100 MHz | U23, BANK2A USRCLK | | Y1 | Crystal Oscillator | 50MHz | crystal input of U14 | | U14 | Programmable |
U14 | Programmable
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| Scroll Title |
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| anchor | Table_OBP_CLK_PO |
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| title | Programmable Oscillator connections |
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|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
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| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
|
| Signals | Clock Type | In/ Out | Connected to | Frequency | Note |
|---|
IN0_P IN0_N | Differential | In In | Oscillator, U15 GND | 25 MHz |
| | IN1..3 | Differential | In | B2B, J3 | Variable |
| XA, XB | Differential |
| Oscillator, U17Y1 GND | 48 50 MHz |
| CLK0 | Differential | Out | Intel Cyclon 10 GX (U23)- Bank 2A | User | Default off | CLK1...4 | Differential | Out | B2B, J3 | User | Default off | | REFCLK_EMIFP | Differential | Out | Intel Cyclon 10 GX (U23)- Bank 3B | User | Default off | | CLK6...7 | Differential | Out | Intel Cyclon 10 GX (U23)- Bank 1D | User | Default off | | CLK8...9 | Differential | Out | Intel Cyclon 10 GX (U23)- Bank 1C | User | Default off | - Bank 1C | User | Default off |
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CryptoAuthentication
ATECC608A (U19) is a CryptoAuthentication device connected to the I2C bus. This chip is optional, for further description see datasheet of manufacturer.
| Scroll Title |
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| anchor | Table_OBP_EEP |
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| title | I2C Interface of CryptoAuthentication |
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| Scroll Table Layout |
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| orientation | portrait |
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| sortDirection | ASC |
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| repeatTableHeaders | default |
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| sortByColumn | 1 |
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| sortEnabled | false |
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| cellHighlighting | true |
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| Schematic | U19 Pin | B2B | U18 Intel Max 10 Pin | Notes |
|---|
| I2C_SCL | SCL | J3-135 | Bank 2 - K2 | - | | I2C_SDA | SDA | J3-137 | Bank 2 - L2 | - |
|
Power and Power-On Sequence
...
| Scroll Title |
|---|
| anchor | Table_RH_HRH |
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| title | Hardware Revision History |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| Date | Revision | Changes | Documentation Link |
|---|
| 2019-09-11 | 02 | - added 100MHz MEMS oscillator, remove CLKUSR signal from J2
- replaced U21/U15 by SiT8008
- added pull-up to M10_NSTATUS signal
- added pull-up to M10_DEVCLRN, removed signal from J2
- added optional CryptoAuthentication chip U19
| REV02 | | 2018-08-10 | 01 | - | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
| Scroll Title |
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| anchor | Figure_RV_HRN |
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| title | Board hardware revision number. |
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|
| Scroll Ignore |
|---|
| draw.io Diagram |
|---|
| border | true |
|---|
| viewerToolbar | true |
|---|
| |
|---|
| fitWindow | false |
|---|
| diagramName | TEI0006_RV_RHN |
|---|
| simpleViewer | false |
|---|
| width | |
|---|
| diagramWidth | 197178 |
|---|
| revision | 13 |
|---|
|
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| Scroll Only |
|---|
| scroll-pdf | true |
|---|
| scroll-office | true |
|---|
| scroll-chm | true |
|---|
| scroll-docbook | true |
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| scroll-eclipsehelp | true |
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| scroll-epub | true |
|---|
| scroll-html | true |
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| 
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| Scroll Title |
|---|
| anchor | Table_RH_DCH |
|---|
| title | Document change history. |
|---|
|
| Scroll Table Layout |
|---|
| orientation | portrait |
|---|
| sortDirection | ASC |
|---|
| repeatTableHeaders | default |
|---|
| sortByColumn | 1 |
|---|
| sortEnabled | false |
|---|
| cellHighlighting | true |
|---|
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| Date | Revision | Contributor | Description |
|---|
| Page info |
|---|
| infoType | Modified date |
|---|
| dateFormat | yyyy-MM-dd |
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| type | Flat |
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| | Page info |
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| infoType | Current version |
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| prefix | v. |
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| type | Flat |
|---|
| showVersions | false |
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| | Page info |
|---|
| infoType | Modified by |
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| type | Flat |
|---|
| showVersions | false |
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|
| | 2019-06-14 | v.80 | Pedram Babakhani | Figures updated - Technical specifications updated
| | v.69 | Pedram Babakhani | | -- | all | | Page info |
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| infoType | Modified users |
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| type | Flat |
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| showVersions | false |
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