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anchor | Figure_OV_BD |
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title | TExxxx block diagram |
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draw.io Diagram |
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border | true |
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viewerToolbar | true |
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fitWindow | false |
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diagramName | TEI0023_Block-diagram |
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simpleViewer | false |
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width | |
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diagramWidth | 642 |
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revision | 1 |
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| Create DrawIO object here: Attention if you copy from other page, objects are only linked. |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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anchor | Figure_OV_MC |
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title | TExxxx main components |
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draw.io Diagram |
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border | true |
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viewerToolbar | true |
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fitWindow | false |
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diagramName | TEI0023-Main_Components |
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simpleViewer | false |
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width | |
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diagramWidth | 642641 |
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revision | 34 |
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Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
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SMA Connector, J5...6
Amplifier, U12
Series Voltage Reference, U8
Analog to Digital Converter, U6
Voltage Regulator, U4 - U10 - U13 - U1U166
Switching Voltage Regulator, U11 - U4
SDRAM Memory, U2
- Intel® MAX 10, U1
SPI Flash Memory, U5
12.00 MHz MEMS oscillatorOscillator, U7 - U19
FTDI USB2 to JTAG/UART adapter, U3
User LEDs, D2...9
FTDI configuration EEPROM, U9
Configuration/Status LED (Red) , D10
Power-on LED (Green), D1
Push button, S1...2
Micro USB Connector, J9
1x14 pin header, J2 (Not assembled)
1x6 pin header, J4 (Not assembled)
1x4 Header, J3 (Not assembled)
1x14 pin header, J1 (Not assembled)
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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widths | |
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cellHighlighting | true |
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Storage device name | Content | Notes |
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Quad SPI Flash | Not Programmed |
| EEPROM | Programmed | FTDI configuration | SDRAM | Not ProgrammedSystem Controller CPLD |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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The FPGA configuration for Intel MAX 10 FPGAs can be stored through JTAG interface either in external configuration device (QSPI flash memory U5) or on the FPGA itself since the Intel MAX 10 FPGA offers non-volatile memory on chip. The FPGA configuration is loaded from the non-volatile memory when the board is powered up.
To configure the FPGA directly, the JTAG interface can be used to configure the FPGA volatile, means the configuration is lost after power off.
Reset process must be done by pressing push button S1.
Scroll Title |
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anchor | Table_OV_BP |
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title | Boot process. |
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Signal | Push Button | Pin Header | Note |
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RESET | S1 | J2 | Connected to nCONFIG |
MODE Signal State | Boot Mode
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anchor | Table_OV_RST |
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title | Reset process. |
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orientation | portrait |
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sortDirection | ASC |
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style | |
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widths | |
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