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At the moment [09.01.2020] it is just understood which files are necessary
to boot a Linux or an bare metal application onto the HPS of a Cyclone 5 / 10 or Aria chip
Requirements
All steps to format / setup a bootable SD card can only be performed within a Linux installation.
(Windows Subsystem for Linux is not capable to format a SD card)
Soweit ist das folgende wohl überflüssig, da schon erwähnt auf den Seiten zuvor:--------------
An installation of INTEL SoC FPGA EMBEDDED DEVELOPMENT SUITE, so the tools
bsp-editor, alt-boot-disc-util and SoC EDS Command Shell are present.
Background
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DIE GRAFIK GEHÖRT INTEL; DARF DIE HIER ÜBERHAUPT SEIN?---------------------------------------------------------
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Partitions within the SD card
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Before writing data to the partitions, unmount the device
sudo umount /dev/sdX*
and plage the SD card in and out of the card reader.
W95 Fat32 partition
The W95 Fat32 partition needs to be formated.
sudo umount /dev/sdX*
sudo mkfs -t vfat /dev/sdXp (p=partition number, needs to be 1)
After the operation finishes, use a data browser to copy the
Linux kernel / zImage(.bin) and the device tree blob / socfpga.dtb.
ext(2/3/4) partition
The ext(2/3/4) partition is formated via:
sudo mkfs.ext3 /dev/sdXp (p=partition number, should be 2)
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Extract the ... .tar.gz file to the partition:
sudo tar -xvf pathToCompressed.tar.gz -C /mnt/card/ (x=decompress v=show progress -C=extract to)
sudo sync (imported, empty all buffers)
a2 partition
This partition need no formatting, the data needs to be copied with the tool
alt-boot-disk-util .
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rootfs loading - Welcome to Poky (Yocto Project Reference Distro) 2.7.2 (warrior)!
Linux - Poky (Yocto Project Reference Distro) 2.7.2 arrow-sockit ttyS0
U-Boot SPL 2013.01.01 (Jan 02 2020 - 11:23:24)
BOARD : Altera SOCFPGA Cyclone V Board
CLOCK: EOSC1 clock 25000 KHz
CLOCK: EOSC2 clock 25000 KHz
CLOCK: F2S_SDR_REF clock 0 KHz
CLOCK: F2S_PER_REF clock 0 KHz
CLOCK: MPU clock 600 MHz
CLOCK: DDR clock 333 MHz
CLOCK: UART clock 100000 KHz
CLOCK: MMC clock 50000 KHz
CLOCK: QSPI clock 400000 KHz
RESET: COLD
INFO : Watchdog enabled
SDRAM: Initializing MMR registers
SDRAM: Calibrating PHY
SEQ.C: Preparing to start memory calibration
SEQ.C: CALIBRATION PASSED
SDRAM: 2048 MiB
ALTERA DWMMC: 0
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