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Table of Contents

Overview

Basic instructions to work with TEI0022.

Functionality of buttons, DIP switches, and LEDs depends on CPLD Firmware.

Board Overview

Board Overview

NumberNoteNumberNote
1U10 - Intel Cyclone V15J5 - Micro USB for UART
2U26...27 - DDR3 for Fabric16U21 - USB to JTAG FTDI

3

U28...29 - DDR3 for HPS17J13 - Micro USB for JTAG
4J4 - FMC18J7...10 / J15 / J17...18 - SMA Connector
5P1...4 - PMOD19S1, S3...5 - Button
6J3 - SD Card20LEDs
7U1 - Ethernet PHY21S2 / S7...8 - DIP Switch
8J1 - Ethernet RJ4522J6 - Power Jack
9U8 - USB PHY23U48 - Oscillator
10U33 - USB HUB24U3 - Programmable Clock Generator
11J2/ J12 - USB Connector25U6 - QSPI
12U23 - HDMI Transmitter26U15 - QSPI
13J11 - HDMI Connector27U54 - Power Monitoring
14U41 - Intel MAX 1028U38 - EEPROM

Power supply

Single +12.0 V power supply is needed to power on the board at power jack J6. Current depends mainly on design and cooling solution. Use Intel Power Estimator and/or your Intel Quartus Prime Project to estimate min current. Minimum of 3A are recommended for basic functionality.

DIP-Switches and Push Buttons

There are three four-bit dip switches and four buttons, explained in the following:

Overview 21DefaultDescriptionActive Level
S2-1OFFHPS User Switch 1L
S2-2OFFHPS User Switch 2L
S2-3OFFFPGA User Switch 1L
S2-4OFFFPGA User Switch 2L
DIP Switche S2

Overview 21DefaultDescriptionActive Level
S7-1OFF
S7-1S7-2Boot Selection
00FPGA
10SD/MMC
11SPI
L
S7-2ONL
S7-3ON
S7-3S7-4S8-4JTAG Selection
XXONMAX 10
ONONOFFHPS
ONOFFOFFFPGA
OFFONOFFFMC
L
S7-4OFFL
DIP Switche S7 (Firmware dependent)

Overview 21DefaultDescriptionActive Level
S8-1OFF
S8-3S8-2S8-1Output Voltage
ONONON3.3 V
ONONOFF2.5 V
ONOFFON1.8 V
ONOFFOFF1.5 V
OFFONON1.25 V
OFFONOFF1.2 V
OFFOFFON0.8 V (not supported by Intel Cyclone V)
OFFOFFOFFSelected by HPS (Firmware dependent)
L
S8-2OFFL
S8-3OFFL
S8-4OFF
S7-3S7-4S8-4JTAG Selection
XXONMAX 10
ONONOFFHPS
ONOFFOFFFPGA
OFFONOFFFMC
H
DIP Switche S8 (Firmware dependent)

Overview 21DefaultDescriptionActive Level
S1OFF

Intel Cyclone V HPS Reset

L
S3OFFIntel Cyclone V HPS Warm ResetL
S4OFFIntel Cyclone V FPGA ResetL
S5OFF

Intel Cyclone V User Button

L
Push Button (Firmware dependent)

LEDs

The LED functionality is explained in the following:

DesignatorColorConnected toActive LevelNote
J1CYellowEthernet PHYLEthernet Status
D25RedIntel MAX 10HBoard Status
D11GreenIntel Cyclone V HPSHHPS User LED 2
D12GreenIntel Cyclone V HPSHHOS User LED 1
D13GreenIntel Cyclone V FPGAHFPGA User LED 2
D14GreenIntel Cyclone V FPGAHFPGA User LED 1
D8GreenIntel MAX 10 and Intel Cyclone VLProgramming Status
D15GreenUART FTDILUART Status
D18GreenUART TXLUART TX Status
D19GreenUART RXLUART RX Status
D21Green+12.0VH+12.0 V Status
D1Green+12.0V_FMCH+12.0 V FMC Status
D2Green+5.0VH+5.0 V Status
D3Green+3.3VH+3.3 V Status
D20Green+3.3V_MAX10H+3.3 V Standby Status
D22Green+3.3V_FMCH+3.3 V FMC Status
D4Green+2.5VH+2.5 V Status
D5GreenIntel MAX 10H+1.8 V Status
D7GreenIntel MAX 10HVCC Status
D9GreenIntel MAX 10HVADJ Status
D6GreenIntel MAX 10HFPGA DDR VDD Status
D23GreenIntel MAX 10HHPS DDR VDD Status
D17GreenIntel MAX 10HHPS DDR VTT Status
D10GreenIntel MAX 10HFPGA DDR VTT Status
LEDs (Firmware dependent)

JTAG/UART

JTAG and UART connections are available through mini USB connectors.

Designator

Connected to

DirectionNote
J13Intel MAX 10 via FTDIINJTAG
J5Intel Cyclone V via FTDI-UART
JTAG and UART

Reference Designs

  • TEI0022 Reference Designs

Notes




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