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DIE GRAFIK GEHÖRT INTEL; DARF DIE HIER ÜBERHAUPT SEIN?---------------------------------------------------------

The steps

BSP Editor

The BSP-Editor takes the handoff folder and generates further source and configuration files to be able to compile
the U-Boot Preloader and U-Boot Bootloader for the HPS.

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Generate   - .dtb or .dts file from .sopcinfo file

Cc:\intelFPGA\18.1\embedded\examples\hardware\cv_soc_devkit_ghrd\tgz\soc_system_18_1_09132018_94307.tar.gz

To generate the .dtb file, a folder containing the Golden Hardware Reference Design for Cyclone 5 FPGA's is required. A copy of it is
part of Intels SoC FPGA Embedded Development Suite. To be on the safe side, copy the file

soc_system_18_1_09132018_94307.tar.gz
inside the folder
c:\intelFPGA\18.1\embedded\examples\hardware\Extract to your project folder via:
mkdir c:/temp/Project/ghrd_cyc5
cp c:/intelFPGA/18.1/embedded/examples/hardware/cv_soc_devkit_ghrd/tgz/soc_system_18_1_09132018_94307.tar.gz c:/temp/Project/ghrd_cyc5\tgz\
to new folder inside your project directory, for example,
c:\Project\ghrd_cyc5
via a file browser.

Use a SoC EDS SHell with administrative privileges to navigate to your newly folder
    cd c:cd c:/temp/Project/ghrd_cyc5
and extract the .tar.gz archieve .
    tar xvf soc_system_18_1_09132018_94307.tar.gzgz    (Decompress the archieve)

Copy the file

Das Programm "Device Tree Generator" / sopc2dts erzeugt ihn.Unter "C:\intelFPGA\18.1\embedded\examples\hardware" findet sich das ghrd / Golden hardware standard
nach z.b.
driveLetter/PathToFolder/cv_soc_devkit_ghrd
entpacken

Aus dem Projekt nach nutzung des "Platform designers" , die erzeugt ....sopinfo in den Ordner kopieren.

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