Page History
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Template Revision 2.2 8 - on construction Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board" |
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Notes :
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Excerpt |
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Release Notes and Release Notes and Know Issues
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Hardware
Hardware
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Additional HW Requirements:
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Additional HW Requirements:
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Notes :
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Reference Design is available on:
Design Flow
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- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setupto start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see alsoTE Board Part Files
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported HDFXSA
- HDF is XSAis exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- HDF is XSAis exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default<ddr size>" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDKVitis
- Run on Vivado TCL: TE::sw_run_hsivitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdkvitis
Note: See SDK Projects TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_hsivitis -all
Launch
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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console:
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
Optional " TE::pr_program_flash_binfile -swapp hello_teb0911" possibleu-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
Optional "TE::pr_program_flash_binfile -swapp hello_teb0911" possible - Copy image.ub and optional misc/sd/init.sh on SD-Card
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Insert SD-Card
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- Copy image.ub, Boot.bin and misc/sd/init.sh on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on CPLD Firmware, see SC0911 CPLD#BootMode
- Insert SD-Card in SD-Slot.
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# GT Clocks #B128-1 set_property PACKAGE_PIN N27 [get_ports {PL_MGT_CLK_clk_p[0]}] #B129-1 set_property PACKAGE_PIN J27 [get_ports {PL_MGT_CLK_clk_p[1]}] #B228-1 set_property PACKAGE_PIN J8 [get_ports {PL_MGT_CLK_clk_p[2]}] #B130-1 set_property PACKAGE_PIN E27 [get_ports {PL_MGT_CLK_clk_p[3]}] #B229-1 set_property PACKAGE_PIN E8 [get_ports {PL_MGT_CLK_clk_p[4]}] #B230-1 set_property PACKAGE_PIN B10 [get_ports {PL_MGT_CLK_clk_p[5]}] ## DP set_property PACKAGE_PIN AB1 [get_ports dp_aux_data_in] set_property PACKAGE_PIN V9 [get_ports dp_hot_plug_detect] set_property PACKAGE_PIN AA8 [get_ports dp_aux_data_out] set_property PACKAGE_PIN AA3 [get_ports dp_aux_data_oe_n] set_property IOSTANDARD LVCMOS18 [get_ports dp_*] ## LED set_property PACKAGE_PIN K14 [get_ports {LED[0]}] set_property PACKAGE_PIN K10 [get_ports {LED[1]}] set_property IOSTANDARD LVCMOS18 [get_ports {LED*}] |
Software Design -
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Vitis
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For SDK project creation, follow instructions from:SDK Projects
Application
SDK template in ./sw_lib/sw_apps/ available.
zynqmp_fsbl
TE modified 2018.2 FSBL
Changes:
- Si5345Configuration
- see xfsbl_board.c and xfsbl_board.h, xfsbl_main.c
- Add Si5345-Registers.h, si5345.c, si5345.h, si5338.c, si5338.h, register_map.h
Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL
zynqmp_fsbl_flash
TE modified 2018.2 FSBL
Changes:
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
Note: Remove compiler flags "-Os -flto -ffat-lto-objects" on 2018.2 SDK to generate FSBL
zynqmp_pmufw
Xilinx default PMU firmware.
hello_teb0911
Hello TEB0911 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Activate:
- SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT
U-Boot
Change platform-top.h
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#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000
#define DFU_ALT_INFO_RAM \
"dfu_ram_info=" \
"setenv dfu_alt_info " \
"image.ub ram $netstart 0x1e00000\0" \
"dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
"thor_ram=run dfu_ram_info && thordown 0 ram 0\0"
#define DFU_ALT_INFO_MMC \
"dfu_mmc_info=" \
"set dfu_alt_info " \
"${kernel_image} fat 0 1\\\\;" \
"dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
"thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"
/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif
/*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS 5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR 0x54
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET 0x20
#endif
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Device Tree
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2019.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynq_fsbl_flashTE modified 2019.2 FSBL General:
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General:
Module Specific:
zynqmp_fsbl_flashTE modified 2019.2 FSBL General:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 and SI5345 Configuration
- PCIe reset
zynqmp_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
hello_teb0911
Hello TEB0911 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT
- CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_I2C_EEPROM=y
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
- CONFIG_SYS_I2C_EEPROM_ADDR=0x54
- CONFIG_SYS_I2C_EEPROM_BUS=5
- CONFIG_SYS_EEPROM_SIZE=256
- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
Change platform-top.h
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Device Tree
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/include/ "system-conf.dtsi"
/ {
chosen {
xlnx,eeprom = &eeprom;
};
};
/* USB */
&dwc3_0 {
status = "okay";
dr_mode = "host";
snps,usb3_lpm_capable;
snps,dis_u3_susphy_quirk;
snps,dis_u2_susphy_quirk;
phy-names = "usb2-phy","usb3-phy";
phys = <&lane1 4 0 2 100000000>;
maximum-speed = "super-speed";
};
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/include/ "system-conf.dtsi" / { }; /* USB */ &dwc3_0 { status = "okay"; dr_mode = "host"; }; /* QSPI */ &qspi { #address-cells = <1>; #size-cells = <0>; status = "okay"; flash0: flash@0 { compatible = "jedec,spi-nor"; reg = <0x0>; #address-cells = <1>; #size-cells = <1>; }; }; /* ETH */ &gem3 { phy-handle = <&phy0>; phy0: phy0@1 { device_type = "ethernet-phy"; reg = <1>; }; }; /* SD1 */ &sdhci1 { // disable-wp; no-1-8-v; }; &i2c0 { i2cswitch@76 { // I2C Switch U13 compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x76>; i2c-mux-idle-disconnect; i2c@2 { // FMCD (/dev/i2c-3) #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // FMCE (/dev/i2c-4) #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { // FMCB (/dev/i2c-5) #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // FMCC (/dev/i2c-6) #address-cells = <1>; #size-cells = <0>; reg = <5>; }; i2c@6 { // PLL (/dev/i2c-7) #address-cells = <1>; #size-cells = <0>; reg = <6>; si570_2: clock-generator3@5d { #clock-cells = <0>; compatible = "silabs,si570"; reg = <0x5d>; temperature-stability = <50>; factory-fout = <156250000>; clock-frequency = <78800000>; }; }; }; i2cswitch@77 { // I2C Switch U37 compatible = "nxp,pca9548"; #address-cells = <1>; #size-cells = <0>; reg = <0x77>; i2c-mux-idle-disconnect; i2c@0 { // SFP2 (/dev/i2c-9) #address-cells = <1>; #size-cells = <0>; reg = <0>; }; i2c@1 { // FMCA (/dev/i2c-10) #address-cells = <1>; #size-cells = <0>; reg = <1>; }; i2c@2 { // FMCF (/dev/i2c-11) #address-cells = <1>; #size-cells = <0>; reg = <2>; }; i2c@3 { // SFP0 (/dev/i2c-12) #address-cells = <1>; #size-cells = <0>; reg = <3>; }; i2c@4 { // SFP1 (/dev/i2c-13) #address-cells = <1>; #size-cells = <0>; reg = <4>; }; i2c@5 { // MEM (/dev/i2c-14) // Low frequency to work with CPLD clock-frequency = <100000>; #address-cells = <1>; #size-cells = <0>; reg = <5>; }; eeprom: eeprom@54 { i2c@6 { // DDR4 (/dev/i2c-15) compatible = "atmel,24c08"; #address-cells = <1>; #size-cellsreg = <0><0x54>; reg = <6>}; }; i2c@7i2c@6 { // USBHDDR4 (/dev/i2c-1615) #address-cells = <1>; #size-cells = <0>; reg = <7><6>; }; }; }; /* UNUSED DMA disable */ &lpd_dma_chan1 i2c@7 { // status = "disabled"; }; &lpd_dma_chan2 { USBH (/dev/i2c-16) status = "disabled"; }; &lpd_dma_chan3 { status#address-cells = "disabled"; }<1>; &lpd_dma_chan4 { status = "disabled"; }; &lpd_dma_chan5 { status#size-cells = "disabled"; }<0>; &lpd_dma_chan6 { status = "disabled"; }; &lpd_dma_chan7 { statusreg = "disabled"; }; &lpd_dma_chan8 { <7>; status = "disabled"}; }; }; |
Kernel
Start with petalinux-config -c kernel
ChangesDeactivate:
- # CONFIG_CPU_IDLE IDLE is not set (only needed to fix JTAG Debug issue)
- # CONFIG_CPU_FREQ FREQ is not set (only needed to fix JTAG Debug issue)
- CONFIG_EDAC_CORTEX_ARM64=y (only needed to fix JTAG Debug issue)
Rootfs
Start with petalinux-config -c rootfs
ChangesActivate:
- i2c-tools
Applications
startup
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- tools
Applications
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
Additional Software
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File location <design name>/misc/Si5338/RegisterMapSi5338-*.txtslabtimeproj
General documentation how you work with these project will be available on Si5338
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