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This step guides through the tasks which have to be done inside the Intel SoC Embedded Development Suite. As mentioned in page "Board bring-up overview for TEI0022" this step is for preloader and bootloader generation which should be done in the following next three steps:

• Preparation
• Preloader/Bootloader Generation
• Device Tree Generation

The section "Preparation" describes preparing steps which are necessary for the generation of the preloader and the bootloader which is described in section "Preloader/Bootloader Generation". After that in section "Device Tree Generation" the steps to create the device tree blob is explained.

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Requirements - EIGENTLICH ÜBERFLÜSSIG, da auf Seite 0 geschrieben... . ?!?

All steps to format / setup a bootable SD card can only be performed within a Linux,
(Windows Subsystem for Linux is not capable to format a SD card) the Linux tool fdisk / sfdisk depend on it.

The tools bsp-editor, alt-boot-disc-util and SoC EDS Command Shell are present.
An installation of INTEL SoC FPGA EMBEDDED DEVELOPMENT SUITE along with Intel Quartus Prime Lite, so the tools
bsp-editor, alt-boot-disc-util and SoC EDS Command Shell are present.

Background

The boot process of the HPS consists of several stages:

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DIE GRAFIK GEHÖRT INTEL; DARF DIE HIER ÜBERHAUPT SEIN?---------------------------------------------------------

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Preparation

After compilation of the Intel Quartus project, described on page Intel Quartus Project, the folder "hps_isw_handoff" is existing inside the project folder. Therefore, if this folder does not exist fix the issue and return to this point.

BSP Editor

The BSP-Editor takes the handoff folder and generates further source and configuration files to be able to compile
the U-Boot Preloader and U-Boot Bootloader for the HPS.

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In your project folder, the folder - software - appears.

U-Boot - Make preloader and main bootloader

The handoff folder contains now after the previous steps all the sources to compile the booot loaders.

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To generate the main U-Boot boot loader, type:
    make uboot                  (Places the image u-boot.img into softwae/spl_bsp/uboot-socfpga)

Device Tree Blob

Lastly, the Device Tree Blob must be generated, whereby Linux can start automated without user interaction.

It acts as an Interface from the board hardware to the Linux Kernel. The .dtb file informs the Linux Kernel about the existing Hardware,
its Configuration and which driver to use for controlling it.

Generate   - .dtb or .dts file from .sopcinfo file

c:\intelFPGA\18.1\embedded\examples\hardware\cv_soc_devkit_ghrd\tgz\soc_system_18_1_09132018_94307.tar.gz

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Use a SoC EDS SHell with administrative privileges to navigate to your newly folder
    cd c:/Project/ghrd_cyc5
and extract the .tar.gz archieve .
    tar xvf soc_system_18_1_09132018_94307.tar.gz    (Decompress the archieve)

Copy the file HPSexample.sopinfosopcinfo from the project folder into this subfolder (c:/Project/ghrd_cyc5).

Enter into the Shell the following command:
sopc2dts --input HPS.sopcinfo --output DTBsocfpga.dtb --type dtb --board hps_common_board_info.xml --bridge-removal all --clocks

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In case a .dts file is desired, use this command:
sopc2dts -i HPS.sopcinfo -o DTBsocfpga.dts -t dts --board hps_common_board_info.xml --bridge-removal all --clocks

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$ sopc2dts.exe --input PlatformEditorHPS.sopcinfo --output DTBsocfpga.dts --type dts --board hps_common_board_info.xml

--bridge-removal all --clocks

MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null

MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null

DTAppend: Unable to find parent, null, for #address-cells. Adding to root

DTAppend: Unable to find parent, null, for #size-cells. Adding to root

DTAppend: Unable to find parent, null, for reg. Adding to root

DTAppend: Unable to find parent, null, for spi-max-frequency. Adding to root

DTAppend: Unable to find parent, null, for m25p,fast-read. Adding to root

DTAppend: Unable to find parent, null, for page-size. Adding to root

DTAppend: Unable to find parent, null, for block-size. Adding to root

DTAppend: Unable to find parent, null, for tshsl-ns. Adding to root

DTAppend: Unable to find parent, null, for tsd2d-ns. Adding to root

DTAppend: Unable to find parent, null, for tchsh-ns. Adding to root

DTAppend: Unable to find parent, null, for tslch-ns. Adding to root

DTAppend: Unable to find parent, null, for cdns,page-size. Adding to root

DTAppend: Unable to find parent, null, for cdns,block-size. Adding to root

DTAppend: Unable to find parent, null, for cdns,read-delay. Adding to root

DTAppend: Unable to find parent, null, for cdns,tshsl-ns. Adding to root

DTAppend: Unable to find parent, null, for cdns,tsd2d-ns. Adding to root

DTAppend: Unable to find parent, null, for cdns,tchsh-ns. Adding to root

DTAppend: Unable to find parent, null, for cdns,tslch-ns. Adding to root

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Decompile - .dtb file to .dts file

C:\intelFPGA\18.1\embedded\host_tools\gnu\dtc\   dtc.exe

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dtc -I dts -O dtb -o device-tree.dtb devicetree.dts

Generate   - .dts file to .dtb file

cd /cygdrive/c/intelFPGA/18.1/embedded/host_tools/gnu/dtc

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