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A 25.000000 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks. It is possible to use the clocks connected to the GTR bank in the user's logic design. This is achieved by instantiating a IBUFDSGTE buffer in the design.
Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.
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2020-02-03 | v.85 | Martin Rohrmüller |
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2019-11-28 | v.81 | Martin Rohrmüller |
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2019-10-30 | v.80 | John Hartfiel |
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2019-09-17 | v79 | Martin Rohrmüller |
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2019-07-17 | v.78 | Martin Rohrmüller |
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2019-05-08 | v.77 | John Hartfiel |
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2018-11-12 | v.74 | John Hartfiel |
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2018-08-30 | v.73 | John Hartfiel |
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2018-07-12 | v.69 | Ali Naseri |
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2018-06-11 | v.61 | John Hartfiel |
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2018-03-12 | v.54 |
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2017-11-20 | v.51 | John Hartfiel |
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2017-11-10 | v.50 | John Hartfiel |
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2017-10-18 | v.49 | John Hartfiel |
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2017-09-25 | v.48 | John Hartfiel |
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2017-09-18 | v.47 | John Hartfiel |
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2017-08-30 | v.46 | Jan Kumann |
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2017-08-24 | v.36 | John Hartfiel |
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2017-08-21 | v.34 | John Hartfiel |
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2017-08-21 | v.33 | Jan Kumann |
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| v.7 | John Hartfiel |
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2017-08-07 | v.5 | Jan Kumann |
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