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Template Revision 2.12
- Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM" - Carrier: TRM Name usually "TEB Series Name" +TRM
Example: "TEB0728 TRM"
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Important General Note:
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Table of Contents |
Overview
The Trenz Electronic TE0821-01-3BI21FA is a powerful 4 x 5 cm MPSoC module with a Xilinx Zynq UltraScale + ZU3EG. In addition, the module is equipped with a 2 GB DDR4 SDRAM chip, 128 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. Robust high-speed connectors provide a large number of inputs and outputs.
This module is pin compatible with Trenz Electronic TE0820 MPSoC modules (JM2 pin 100 is not connected).
The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.
All components cover at least the industrial temperature range from -40 ° C to + 85 ° C. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.
Refer to http://trenz.org/te0821-info for the current online version of this manual and other available documentation.
Key Features
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Note: 'description: Important components and connector or other Features of the module → please sort and indicate assembly options Key Features' must be split into 6 main groups for modules and mainboards: - SoC/FPGA
- Package: SFVC784
- Device: ZU2...ZU5*
- Engine: CG, EG, EV*
- Speed: -1LI, -2LE,*, **
- Temperature: I, E,*, **
- RAM/Storage
- Low Power DDR4 on PS
- Data width: 32bit
- Size: def. 2GB*
- Speed:***
- eMMC
- Data width: 8Bit
- size: def. 8GB *
- QSPI boot Flash in dual parallel mode (size depends on assembly version)
- Data width: 8bit
- size: def. 128MB *
- HyperRAM/Flash (optional, default not assembled)
- MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
- On Board
- Lattice LCMXO2
- PLL SI5338
- Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
- Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3320C)
- Interface
- 132 x HP PL I/Os (3 banks)
- ETH
- USB
- 4 GTR (for USB3, Sata, PCIe, DP)
- MIO for UART
- MIO for SD
- MIO for PJTAG
- JTAG
- Ctrl
- Power
- 3.3V-5V Main Input
- 3.3V Controller Input
- Variable Bank IO Power Input
- Dimension
- Notes
- * depends on assembly version
- ** also non low power assembly options possible
- *** depends on used U+ Zynq and DDR4 combination
Key Features' must be split into 6 main groups for carrier: - Modules
- TE0808, TE807, TE0803,...
- RAM/Storage
- On Board
- Interface
- E.g. ETH, USB, B2B, Display port
- Power
- E.g. Input supply voltage
- Dimension
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- SoC/FPGA
- Xilinx Zynq UltraScale+ XCZU3EG-1SFVC784I
- ZU3EG, 784 Pin Packages
- Application Processor: Quad-Core ARM Cortex-A53 MPCore
- Real-Time Processor: Dual-core ARM Cortex-R5 MPCore
- Graphics Processor: Mali-400 MP2
- RAM/Storage
- 2 GByte DDR4 SDRAM, 32-Bit databus-width
- 128 MByte QSPI boot Flash in dual parallel mode
- 8 GByte e.MMC Memory (up to 64 GByte)
- MAC address serial EEPROM with EUI-48 node identity
- On Board
- Graphic Processing Unit (GPU) :Mali-400 MP2
- Interface
- Power
- All power supplies on board
- Dimension
Block Diagram
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anchor | Figure_OV_BD |
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title | TE0821 block diagram |
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Main Components
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Notes : - Picture of the PCB (top and bottom side) with labels of important components
- Add List below
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anchor | Figure_OV_MC |
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title | TE0821 main components |
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- Xilinx Zynq UltraScale+ XCZU3EG, U1
- Red LED (ERR_OUT), D3
- Green LED (ERR_STATUS), D4
- Red LED (DONE), D1
- 10/100/1000 Mbps energy efficient ethernet transceiver, U8
- 8Gb DDR4, U2-U3
- 512 Mbit QSPI flash memory, U7-U17
- B2B connector Samtec Razor Beam, JM1
- Green User LED, D2
- Programmable clock generator, U10
- USB2.0 Transceiver, U18
- B2B connector Samtec Razor Beam, JM3
- B2B connector Samtec Razor Beam, JM2
- 8 GByte eMMC memory, U6
- Lattice Semiconductor MachXO2 System Controller CPLD, U21
Initial Delivery State
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Notes : Only components like EEPROM, QSPI flash can be initialized by default at manufacture. If there is no components which might have initial data ( possible on carrier) you must keep the table empty |
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anchor | Table_OV_IDS |
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title | Initial delivery state of programmable devices on the module |
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orientation | portrait |
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Storage device name | Content | Notes |
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QSPI Flash Memory | Not programmed |
| eMMC Memory | Not programmed |
| Programmable Clock Generator | Not programmed |
| CPLD (LCMXO2-256HC) | SC0820-02 QSPI Firmware |
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Configuration Signals
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- Overview of Boot Mode, Reset, Enables.
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Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.
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anchor | Table_OV_BP |
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title | Boot process. |
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MODE Pin | Boot Mode |
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Low | QSPI | High | SD Card |
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anchor | Table_OV_RST |
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title | Reset process. |
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orientation | portrait |
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Signal | B2B | I/O | Note |
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EN | JM1-28 | Input | CPLD Enable Pin |
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Signals, Interfaces and Pins
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Notes : - For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
- For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
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Board to Board (B2B) I/Os
FPGA bank number and number of I/O signals connected to the B2B connector:
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anchor | Table_SIP_B2B |
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title | General PL I/O to B2B connectors information |
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FPGA Bank | Type | B2B Connector | I/O Signal Count | Voltage Level | Notes |
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24 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 25 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 26 | HD | JM1 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 44 | HD | JM2 | 24x I/O, 12x LVDS Pairs | Variable | Max voltage 3.3V | 65 | HP | JM2 | 18x I/O, 9x LVDS Pairs | Variable | Max voltage 1.8V | 65 | HP | JM3 | 16x I/O, 8x LVDS Pairs | Variable | Max voltage 1.8V | 505 | GTR | JM3 | 16x I/O, 8x LVDS Pairs | - | 4x lanes | 505 | GTR CLK | JM3 | 1x Diff Clock | - |
| 501 | MIO | JM1 | 15 I/O | 3.3V |
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JTAG Interface
JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD through B2B connector JM2.
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anchor | Table_SIP_JTG |
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title | JTAG pins connection |
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orientation | portrait |
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JTAG Signal | B2B Connector | Note |
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TMS | JM2-93 |
| TDI | JM2-95 |
| TDO | JM2-97 |
| TCK | JM2-99 |
| JTAGEN | JM1-89 | Pulled Low: Xilinx Zynq UltraScale+ MPSoC Pulled High: Lattice MachXO CPLD |
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MGT Lanes
There are 4x MGT Lanes connected to FPGA Bank 505-GTR.
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anchor | Table_SIP_MGT |
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title | MGT Lanes connection |
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orientation | portrait |
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sortDirection | ASC |
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Lane | Schematic | B2B | Note |
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0 | - B505_RX0_P
- B505_RX0_N
- B505_TX0_P
- B505_TX0_N
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| 1 | - B505_RX1_P
- B505_RX1_N
- B505_TX1_P
- B505_TX1_N
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| 2 | - B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
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| 3 | - B505_RX2_P
- B505_RX2_N
- B505_TX2_P
- B505_TX2_N
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Gigabit Ethernet
On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.
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anchor | Table_SIP_ETH |
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title | GigaBit Ethernet connection |
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orientation | portrait |
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Pin | Schematic | Connected to | Note |
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MDIP0...3 | PHY_MDI0...3 | B2B, JM1 |
| MDC | ETH_MDC | MIO76 |
| MDIO | ETH_MDIO | MIO77 |
| S_IN | S_IN | B2B, JM3 |
| S_OUT | S_OUT | B2B, JM3 |
| TXD0..3 | ETH_TXD0...3 | MIO65...68 |
| TX_CTRL | ETH_TXCTL | MIO69 |
| TX_CLK | ETH_TXCK | MIO64 |
| RXD0...3 | ETH_RXD0...3 | MIO71...74 |
| RX_CTRL | ETH_RXCTL | MIO75 |
| RX_CLK | ETH_RXCK | MIO70 |
| LED0...2 | PHY_LED0...2 | FPGA Bank 66 |
| RESETn | ETH_RST | MIO24 |
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MIO Pins
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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin | Connected to | B2B | Notes |
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MIO12...14 | SPI_CS , SPI_DQ0... SPI_DQ3, SPI_SCK | J2 | QSPI |
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anchor | Table_SIP_MIOs |
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title | MIOs pins |
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orientation | portrait |
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sortDirection | ASC |
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MIO Pin | Connected to | B2B | Notes |
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0...5 | QSPI Flash, U7 | - | SPI Flash | 7...12 | QSPI Flash, U17 | - | SPI Flash | 13...23 | eMMC, U6 |
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| 24 | ETH Transceiver, U8 | - | ETH_RST | 25 | USB2.0 Transceiver, U18 | - | OTG_RST | 26...33 | User MIO | JM1 |
| 34...37 | N.C | - | N.C | 38...39 | EEPROM, U25 | - | I2C_SDA/SCL | 40...45 | N.C |
| N.C | 46...51 | SD Card | JM1 |
| 52...63 | USB2.0 Transceiver, U18 | - |
| 63...77 | Ethernet Transceiver, U8 | - |
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Test Points
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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point | Signal | B2B | Notes |
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10 | PWR_PL_OK | J2-120 |
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anchor | Table_SIP_TPs |
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title | Test Points Information |
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orientation | portrait |
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Test Point | Signal | Connected to | Notes |
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1 | I2C_SCL | EEPROM, U25 |
| 2 | I2C_SDA | EEPROM, U25 |
| 3 | SRST_B | FPGA Bank 503 | PSCONFIG | 4 | PS_CLK | FPGA Bank 503 | PSCONFIG | 5 | PROG_B | FPGA Bank 503 | PSCONFIG | 6 | INIT_B | FPGA Bank 503 | PSCONFIG | 7 | DONE | Red LED, D1 |
| 8 | PS_LP0V85 | Voltage Regulator, U12 |
| 9 | DDR_2V5 | Voltage Regulator, U4 |
| 10 | PS_AVCC | Voltage Regulator, U9 |
| 11 | DDR_1V2 | Voltage Regulator, U15 |
| 12 | PS_AVTT | Voltage Regulator, U3 |
| 13 | PS_FP0V85 | Voltage Regulator, U26 |
| 14 | POR_B | Voltage Translator, U19 |
| 15 | PS_PLL | Voltage Regulator, U23 |
| 16 | PL_VCCINT | Voltage Regulator, U5 |
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On-board Peripherals
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Notes : - add subsection for every component which is important for design, for example:
- Two 100 Mbit Ethernet Transciever PHY
- USB PHY
- Programmable Clock Generator
- Oscillators
- eMMCs
- RTC
- FTDI
- ...
- DIP-Switches
- Buttons
- LEDs
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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection |
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anchor | Table_OBP |
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title | On board peripherals |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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cellHighlighting | true |
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Quad SPI Flash Memory
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Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options. |
The TE0821 is equipped with dual Flash Memory, U7, U17.
Scroll Title |
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anchor | Table_OBP_SPI |
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title | Quad SPI interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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Pin | Schematic | Notes |
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U7 Pin | U17 Pin |
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nCS | MIO5 | MIO7 |
| CLK | MIO0 | MIO12 |
| DI/IO0 | MIO4 | MIO8 |
| DO/IO1 | MIO1 | MIO9 |
| nHOLD/IO3 | MIO3 | MIO11 |
| WP/IO2 | MIO2 | MIO10 |
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EEPROM
There is a 2Kb EEPROM provided on the module TE0821.
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anchor | Table_OBP_EEP |
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title | I2C EEPROM interface MIOs and pins |
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orientation | portrait |
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sortDirection | ASC |
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MIO Pin | Schematic | U25 Pin | Notes |
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MIO39 | I2C_SDA | SDA |
| MIO38 | I2C_SCL | SCL |
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anchor | Table_OBP_I2C_EEPROM |
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title | I2C address for EEPROM |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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MIO Pin | I2C Address | Designator | Notes |
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MIO38...39 | 0x50 | U25 |
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LEDs
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anchor | Table_OBP_LED |
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title | On-board LEDs |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Color | Connected to | Active Level | Note |
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D1 | Red | DONE | Low |
| D2 | Green | USR_LED | High |
| D3 | Red | ERR_OUT | High |
| D4 | Green | ERR_STATUS | High |
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DDR4 SDRAM
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Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3) |
The TE0821 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.
- Part number: K4A8G165WB-BIRC
- Supply voltage: 1.2V
- Speed: 2400 Mbps
- Temperature: -40 ~ 95 °C
GigaBit Ethernet
Scroll Title |
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anchor | Table_OBP_ETH |
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title | Ethernet PHY to Zynq SoC connections |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Pin | Schematic | Connected to | Note |
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MDIP0...3 | PHY_MDI0...3 | B2B, JM1 |
| MDC | ETH_MDC | MIO76 |
| MDIO | ETH_MDIO | MIO77 |
| S_IN | S_IN | B2B, JM3 |
| S_OUT | S_OUT | B2B, JM3 |
| TXD0..3 | ETH_TXD0...3 | MIO65...68 |
| TX_CTRL | ETH_TXCTL | MIO69 |
| TX_CLK | ETH_TXCK | MIO64 |
| RXD0...3 | ETH_RXD0...3 | MIO71...74 |
| RX_CTRL | ETH_RXCTL | MIO75 |
| RX_CLK | ETH_RXCK | MIO70 |
| LED0...2 | PHY_LED0...2 | FPGA Bank 66 |
| RESETn | ETH_RST | MIO24 |
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Clock Sources
Scroll Title |
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anchor | Table_OBP_CLK |
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title | Osillators |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Designator | Description | Frequency | Note |
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U11 | MEMS Oscillator | 25 MHz |
| U14 | MEMS Oscillator | 52 MHz |
| U32 | MEMS Oscillator | 80 MHz |
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Programmable Clock Generator
There is a programmable clock generator on-board (U10) provided in order to generate variable clocks for the module. Programming can be done using I2C via PIN header J??. The I2C Address is 0x70 or 0x71.
Scroll Title |
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anchor | Table_OBP_PCLK |
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title | Programmable Clock Generator Inputs and Outputs |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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U25 Pin
| Signal | Connected to | Direction | Note |
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IN0..1 | CLK_IN | JM3 | IN |
| IN2 | CLK_25M | Oscillator, U11 | IN |
| SCL | I2C_SCL | EEPROM,U25 | INOUT |
| SDA | I2C_SDA | EEPROM,U25 | INOUT |
| CLK0 | CLK0 | JM3 | OUT |
| CLK1 | B505_CLK3 | FPGA Bank 505 | IN |
| CLK2 | B505_CLK1 | FPGA Bank 505 | IN |
| CLK3 | CLK3_N |
| IN |
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Power and Power-On Sequence
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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn: - Power on-sequence
- Power distribution
- Voltage monitoring circuit
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Power Supply
Power supply with minimum current capability of xx A for system startup is recommended.
Power Consumption
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anchor | Table_PWR_PC |
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title | Power Consumption |
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orientation | portrait |
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sortDirection | ASC |
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style | |
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sortEnabled | false |
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cellHighlighting | true |
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Power Input Pin | Typical Current |
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VIN | TBD* | 3.3VIN | TBD* |
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* TBD - To Be Determined
Power Distribution Dependencies
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anchor | Figure_PWR_PD |
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title | Power Distribution |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TE0821_PWR_PD |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
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diagramDisplayName | |
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lbox | true |
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diagramWidth | 641 |
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revision | 4 |
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Scroll Only |
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Power-On Sequence
Scroll Title |
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anchor | Figure_PWR_PS |
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title | Power Sequency |
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Scroll Ignore |
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draw.io Diagram |
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border | false |
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diagramName | TE0821_PWR_PS |
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simpleViewer | false |
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width | |
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links | auto |
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tbstyle | hidden |
---|
diagramDisplayName | |
---|
lbox | true |
---|
diagramWidth | 641 |
---|
revision | 4 |
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|
|
Scroll Only |
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|
|
Power Rails
Scroll Title |
---|
anchor | Table_PWR_PR |
---|
title | Module power rails. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Power Rail Name | B2B JM1 Pin | B2B JM2 Pin | Direction | Notes |
---|
VIN | 1, 3, 5 | 2, 4, 6, 8 | Input | Supply voltage from the carrier board | 3.3V | - | 10, 12 | Output | Internal 3.3V voltage level | 3.3VIN | 13, 15 | - | Input | Supply voltage from the carrier board | 1.8V | 39 | - | Output | Internal 1.8V voltage level | JTAG VREF | - | 91 | Output | JTAG reference voltage. Attention: Net name on schematic is "3.3VIN" | VCCO_64 | - | 7, 9 | Input | High performance I/O bank voltage | VCCO_65 | - | 5 | Input | High performance I/O bank voltage | VCCO_66 | 9, 11 | - | Input | High performance I/O bank voltage |
|
Bank Voltages
Scroll Title |
---|
anchor | Table_PWR_BV |
---|
title | Zynq SoC bank voltages. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
| Schematic Name | | Notes |
---|
64 HP | VCCO_64 | User | HP: 1.0V to 1.8V | 65 HP | VCCO_65 | User | HP: 1.0V to 1.8V | 66 HP | VCCO_66 | User | HP: 1.0V to 1.8V | 500 PSMIO | VCCO_PSIO0_500 | 1.8V | - | 501 PSMIO | VCCO_PSIO1_501 | 3.3V | - | 502 PSMIO | VCCO_PSIO2_502 | 1.8V | - | 503 PSCONFIG | VCCO_PSIO3_503 | 1.8V | - | 504 PSDDR | VCCO_PSDDR_504 | 1.2V | - |
|
Board to Board Connectors
Page properties |
---|
|
- This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series, For example: 6 x 6 SoM LSHM B2B Connectors
Include Page |
---|
| PD:6 x 6 SoM LSHM B2B Connectors |
---|
| PD:6 x 6 SoM LSHM B2B Connectors |
---|
|
|
Include Page |
---|
| PD:4 x 5 SoM LSHM B2B Connectors |
---|
| PD:4 x 5 SoM LSHM B2B Connectors |
---|
|
Technical Specifications
Absolute Maximum Ratings
Scroll Title |
---|
anchor | Table_TS_AMR |
---|
title | PS absolute maximum ratings |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Description | Min | Max | Unit | Notes |
---|
VIN supply voltage | -0.3 | 7 | V | See EN6347QI and TPS82085SIL datasheets | 3.3VIN supply voltage | -0.1 | 3.630 | V | Xilinx DS925 and TPS27082L datasheet | PS I/O supply voltage, VCCO_PSIO | -0.5 | 3.630 | V | Xilinx document DS925 | PS I/O input voltage | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx document DS925 | HP I/O bank supply voltage, VCCO | -0.5 | 2.0 | V | Xilinx document DS925 | HP I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS925 | PS GTR reference clocks absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 | PS GTR absolute input voltage | -0.5 | 1.1 | V | Xilinx document DS925 | Voltage on SC CPLD pins | -0.5 | 3.75 | V | Lattice Semiconductor MachXO2 datasheet | Storage temperature | -40 | +85 | °C | See eMMC datasheet |
|
Recommended Operating Conditions
Operating temperature range depends also on customer design and cooling solution. Please contact us for options.
Scroll Title |
---|
anchor | Table_TS_ROC |
---|
title | Recommended operating conditions. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Parameter | Min | Max | Units | Reference Document |
---|
|
|
| V | See ???? datasheets. |
|
|
| V | See Xilinx ???? datasheet. |
|
|
| °C | See Xilinx ???? datasheet. |
|
|
| °C | See Xilinx ???? datasheet. |
|
Physical Dimensions
PCB thickness: 1.74 mm.
Scroll Title |
---|
anchor | Figure_TS_PD |
---|
title | Physical Dimension |
---|
|
Scroll Ignore |
---|
draw.io Diagram |
---|
border | false |
---|
| |
---|
diagramName | TE0821_TS_PD |
---|
simpleViewer | false |
---|
width | |
---|
links | auto |
---|
tbstyle | top |
---|
diagramDisplayName | |
---|
lbox | true |
---|
diagramWidth | 641 |
---|
revision | 3 |
---|
|
|
Scroll Only |
---|
scroll-pdf | true |
---|
scroll-office | true |
---|
scroll-chm | true |
---|
scroll-docbook | true |
---|
scroll-eclipsehelp | true |
---|
scroll-epub | true |
---|
scroll-html | true |
---|
|
|
|
Currently Offered Variants
Scroll Title |
---|
anchor | Table_VCP_SO |
---|
title | Trenz Electronic Shop Overview |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
|
Revision History
Hardware Revision History
Scroll Title |
---|
anchor | Table_RH_HRH |
---|
title | Hardware Revision History |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Revision | Changes | Documentation Link |
---|
2019-04-26 | REV01 | | REV01 |
|
Hardware revision number can be found on the PCB board together with the module model number separated by the dash.
Scroll Title |
---|
anchor | Figure_RV_HRN |
---|
title | Board hardware revision number. |
---|
|
Scroll Ignore |
---|
draw.io Diagram |
---|
border | false |
---|
| |
---|
diagramName | TE0821_RV_HRN |
---|
simpleViewer | false |
---|
width | |
---|
links | auto |
---|
tbstyle | hidden |
---|
diagramDisplayName | |
---|
lbox | true |
---|
diagramWidth | 326 |
---|
revision | 3 |
---|
|
|
Scroll Only |
---|
|
|
Document Change History
Page properties |
---|
|
- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
|
Scroll Title |
---|
anchor | Table_RH_DCH |
---|
title | Document change history. |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Date | Revision | Contributor | Description |
---|
Page info |
---|
infoType | Modified date |
---|
dateFormat | yyyy-MM-dd |
---|
type | Flat |
---|
|
| Page info |
---|
infoType | Current version |
---|
prefix | v. |
---|
type | Flat |
---|
showVersions | false |
---|
|
| Page info |
---|
infoType | Modified by |
---|
type | Flat |
---|
showVersions | false |
---|
|
| | -- | all | Page info |
---|
infoType | Modified users |
---|
type | Flat |
---|
showVersions | false |
---|
|
| |
|
Disclaimer
Include Page |
---|
| IN:Legal Notices |
---|
| IN:Legal Notices |
---|
|