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The Trenz Electronic TE0821 is a powerful 4 x 5 cm MPSoC module integrated with a Xilinx Zynq UltraScale+ MPSoC. In addition, the module is equipped with 2x 1 GB DDR4 SDRAM chip, 4Gb up to 128 Gb eMMC chip,  2x 64 MB flash memory for configuration and data storage, as well as powerful switching power supplies for all required voltages. The module is equipped with a Lattice Mach XO2 CPLD for system controlling. 3x Robust high-speed connectors provide a large number of inputs and outputs.

The highly integrated modules are smaller than a credit card and are offered in several variants at an affordable price-performance ratio. Modules with a 4 x 5 cm form factor are completely mechanically and largely electrically compatible with each other.

All components cover at least the industrial temperature range. The temperature range in which the module can be used depends on the customer design and the selected cooling. Please contact us for special solutions.

Refer to for the current online version of this manual and other available documentation.

Key Features

  • SoC/FPGA
    • Package: SFVC784
    • Device: ZU2 ...ZU5, *
    • Engine:  EG, CG, EV, *
    • Speed: -1, -1L, -2, -2L, 3, *, **
    • Temperature: I, E, *, **
  • RAM/Storage
    • 2x  DDR4 SDRAM,
      • Data Width: 16 Bit
      • Size: 8 Gb, *
      • Speed: 2400 Mbps, ***
    • 2x QSPI boot Flash in dual parallel mode
      • Data Width: 8 Bit
      • Size: 512 Mb Gb, *
    • 1x e.MMC Memory
      • Data Width: 16 Bit
      • Size: 8 Gb, *
    • MAC address serial EEPROM
  • On Board
    • Lattice MachXO2 CPLD
    • Programmable Clock Generator
    • Hi-speed USB2 ULPI Transceiver
    • 4x LEDS
  • Interface
    • 1 Gbps RGMII Ethernet interface
    • Hi-speed USB2 ULPI transceiver with full OTG support
    • Graphic Processor Mali-400 MP2, *
    • 156 x High Performance (HP) und 96 x High Density PL I/Os
    • 4 x serial PS GTR transceivers
      • PCI Express interface
      • SATA 3.1 interface
      • DisplayPort interface with video resolution up to 4k x 2k

      • 2x USB 3.0 specification compliant interface implementing a 5 Gbit/s line rate
  • Power
    • All power regulators on board
  • Dimension
    • 40 x 50 mm
  • Note
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination
    • Rugged for shock and high vibration

Block Diagram

TE0821 block diagram

Main Components

TE0821 main components
  1. Xilinx ZYNQ UltraScale+ MPSoC, U1
  2. Red LED (ERR_OUT), D3
  3. Green LED (ERR_STATUS), D4
  4. Red LED (DONE), D1
  5. 10/100/1000 Mbps Energy Efficient Ethernet Transceiver, U8
  6. 8Gb DDR4, U2-U3
  7. 512 Mbit QSPI flash memory, U7-U17
  8. Green User LED, D2
  9. B2B connector Samtec Razor Beam, JM1
  10. Programmable clock generator, U10
  11. USB2.0 Transceiver,  U18
  12. B2B connector Samtec Razor Beam, JM3
  13. B2B connector Samtec Razor Beam, JM2
  14. 8 GByte eMMC memory, U6
  15. Lattice Semiconductor MachXO2 System Controller CPLD, U21

Additional assembly options are available for cost or performance optimization upon request.

Initial Delivery State

Storage device name



Dual QSPI Flash Memory

Not programmed

eMMC Memory

Not programmed

DDR4 SDRAMNot programmed
Programmable Clock GeneratorNot programmed
CPLD (LCMXO2-256HC)ProgrammedTE0821 CPLD
Initial delivery state of programmable devices on the module

Configuration Signals

Two different firmware versions are available, one with the QSPI boot option and other with the SD Card boot option.


Boot Mode


LowSD Card*
Boot process.

*changable also with other CPLD Firmware: TE0821 CPLD.




JM1-28InputCPLD Enable Pin
Reset process.

Signals, Interfaces and Pins

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

FPGA BankTypeB2B ConnectorI/O Signal CountVoltage LevelNotes
24HDJM224x I/O, 12x  LVDS PairsVariable Max voltage 3.3V

24x I/O, 12x  LVDS Pairs

Variable Max voltage 3.3V
26HDJM124x I/O, 12x  LVDS PairsVariable Max voltage 3.3V
44HDJM224x I/O, 12x  LVDS PairsVariableMax voltage 3.3V



18x I/O, 9x LVDS Pairs

VariableMax voltage 1.8V




16x I/O, 8x LVDS Pairs


Max voltage 1.8V
505GTRJM316x I/O, 8x LVDS Pairs-4x lanes
505GTR CLKJM31x Diff Clock-




15 I/O


General PL I/O to B2B connectors information

For detailed information about the pin-out, please refer to the Pin-out table.

JTAG Interface

JTAG access to the Xilinx Zynq UltraScale+ is applicable by using Lattice MachXO CPLD  through B2B connector JM2.

JTAG Signal

B2B Connector

JTAGENJM1-89Pulled Low: Xilinx Zynq UltraScale+ MPSoC
Pulled High: Lattice MachXO CPLD
JTAG pins connection

MGT Lanes

There are 4x MGT Lanes connected to FPGA Bank 505-GTR. The Xilinx Zynq UltraScale+ device used on the TE0821 module has 4 GTR transceivers. All 4 are wired directly to B2B connector JM3. MGT (Multi Gigabit Transceiver) lane consists of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:


  • B505_RX0_P
  • B505_RX0_N
  • B505_TX0_P
  • B505_TX0_N
  • JM3-26
  • JM3-28
  • JM3-25
  • JM3-27

  • B505_RX1_P
  • B505_RX1_N
  • B505_TX1_P
  • B505_TX1_N
  • JM3-20
  • JM3-22
  • JM3-19
  • JM3-21

  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-14
  • JM3-16
  • JM3-13
  • JM3-15

  • B505_RX2_P
  • B505_RX2_N
  • B505_TX2_P
  • B505_TX2_N
  • JM3-8
  • JM3-10
  • JM3-7
  • JM3-9

MGT Lanes connection

Gigabit Ethernet

On-board Gigabit Ethernet PHY is provided with Marvell Alaska 88E1512 chip. The Ethernet PHY RGMII interface is connected to the Zynq Ethernet0 PS GEM0. I/O voltage is fixed at 1.8V for HSTL signaling. SGMII (SFP copper or fiber) can be used directly with the Ethernet PHY, as the SGMII pins are available on the B2B connector JM3. The reference clock input of the PHY is supplied from an on-board 25MHz oscillator (U11), the 125MHz output clock is left unconnected.

PinSchematicConnected toNote


B2B, JM1




LED0...2PHY_LED0...2FPGA Bank 66
GigaBit Ethernet connection

System Controller CPLD

Special purpose pins are connected to System Controller CPLD and have following default configuration:

Pin NameModeFunctionDefault Configuration
EN1InputPower Enable

No hard wired function on PCB. When forced low, PGOOD goes low without effect on power management

PGOODOutputPower GoodOnly indirect used for power status, see CPLD description
NOSEQ--No used for Power sequencing, see CPLD description

Active low reset, gated to POR_B

JTAGENInputJTAG SelectLow for normal operation, high for CPLD JTAG access
System Controller CPLD special purpose pins

Please check the entire information at TE0821 CPLD.

USB Interface

USB PHY is provided by Microchip USB3320. The ULPI interface is connected to the Zynq PS USB0. I/O voltage is fixed at 1.8V. Reference clock input for the USB PHY is supplied by the on-board 52.00 MHz oscillator (U14). 

 PHY PinZYNQ PinB2B NameNotes
ULPIMIO52..63-Zynq USB0 MIO pins are connected to the USB PHY.
REFCLK--52.00 MHz from on-board oscillator (U14).
REFSEL[0..2]--Reference clock frequency select, all set to GND selects 52.00 MHz.
RESETBMIO25-Active low reset.
CLKOUTMIO52-Connected to 1.8V, selects reference clock operation mode.
DP, DM-OTG_D_P, OTG_D_NUSB data lines routed to B2B connector JM3 pins 47 and 49.
CPEN-VBUS_V_ENExternal USB power switch active high enable signal, routed to JM3 pin 17.
VBUS-USB_VBUSConnect to USB VBUS via a series of resistors, see reference schematics, routed to JM3 pin 55.
ID-OTG_IDFor an A-device connect to ground, for a B-device left floating. routed from JM3 pin 23.
General overview of the USB PHY signals

I2C Interface

On-board I2C devices are connected to MIO38 (SCL) and MIO39 (SDA) which are configured as I2C0 by default. Addresses for on-board I2C slave devices are listed in the table below:

I2C DeviceI2C AddressNotes

Si5338A PLL

Address table of the I2C bus slave devices

MIO Pins

MIO PinConnected toB2BNotes
0...5QSPI Flash, U7-SPI Flash
7...12QSPI Flash, U17-SPI Flash
13...23eMMC, U6

24ETH Transceiver, U8-ETH_RST
25USB2.0 Transceiver, U18-OTG_RST
26...33User MIOJM1
38...39EEPROM, U25-I2C_SDA/SCL
46...51SD CardJM1
52...63USB2.0 Transceiver, U18-
63...77Ethernet Transceiver, U8-
MIOs pins

Test Points

Test PointSignalConnected toNotes
8PS_LP0V85Voltage Regulator, U12
9DDR_2V5Voltage Regulator, U4
10PS_AVCCVoltage Regulator, U9
11DDR_1V2Voltage Regulator, U15
12PS_AVTTVoltage Regulator, U13
13PS_FP0V85Voltage Regulator, U26
14POR_BVoltage Translator, U19
15PS_PLLVoltage Regulator, U23
16PL_VCCINTVoltage Regulator, U5
Test Points Information

On-board Peripherals

On board peripherals

Quad SPI Flash Memory

The TE0821 is equipped with dual Flash Memory, U7, U17.  Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

U7 PinU17 Pin
Quad SPI interface MIOs and pins


There is a 2Kb EEPROM provided on the module TE0821.

MIO PinSchematicU25 PinNotes
I2C EEPROM interface MIOs and pins

MIO PinI2C AddressDesignatorNotes
I2C address for EEPROM


DesignatorColorConnected toActive LevelNote
On-board LEDs


The TE0821 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

  • Part number: K4A8G165WB-BIRC
  • Supply voltage: 1.2V
  • Speed: 2400 Mbps
  • Temperature: -40 ~ 95 °C

System Controller CPLD

The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0821 System Controller CPLD page

GigaBit Ethernet

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U11).

PinSchematicConnected toNote


B2B, JM1




LED0...2PHY_LED0...2FPGA Bank 66
Ethernet PHY to Zynq SoC connections

USB2.0 Transceiver

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

eMMC Flash Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

Clock Sources

U11MEMS Oscillator25 MHz
U14MEMS Oscillator52 MHz
U32MEMS Oscillator80 MHz

Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I2C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.00 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.

Once running, the frequency and other parameters can be changed by programming the device using the I2C bus connected between the FPGA (master) and clock generator (slave). For this, proper I2C bus logic has to be implemented in FPGA.

U25 PinSignalConnected toDirectionNote


IN2CLK_25MOscillator, U11IN
CLK1B505_CLK3FPGA Bank 505IN
CLK2B505_CLK1FPGA Bank 505IN
Programmable Clock Generator Inputs and Outputs

Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

Power Input PinTypical Current
Power Consumption

* TBD - To Be Determined

Power Distribution Dependencies

Power Distribution

Power-On Sequence

Power Sequency

Power Rails

Power Rail Name

B2B JM1 Pin

B2B JM2 Pin

B2B JM3 Pin



1, 3, 5

2, 4, 6, 8-InputSupply voltage from the carrier board
3.3V-10, 12-OutputInternal 3.3V voltage level
-Input0 to 3.3V Voltage
3.3VIN13, 15--InputSupply voltage from the carrier board
1.8V39--OutputInternal 1.8V voltage level
JTAG VREF-91-OutputJTAG reference voltage.
Attention: Net name on schematic is "3.3VIN"
VCCO_HD24_44-7, 9-Input0 to 3.3V Voltage
VCCO_65-5-Input0 to 1.8V Voltage
PSBATT79--Input1.2 to 1.5V Voltage
Module power rails.

Bank Voltages

FPGA BankSchematicVoltageNote
Bank 24 HDVCCO_HD24_44Variable Max voltage 3.3V
Bank 25 HDVCCO_HD25_26Variable Max voltage 3.3V
Bank 26 HDVCCO_HD25_26Variable Max voltage 3.3V
Bank 44 HDVCCO_HD24_44VariableMax voltage 3.3V
Bank 64 HPVCCO_64N.CNot Connected
Bank 65 HP


VariableMax voltage 1.8V
Bank 66 HPVCCO_661.8V
Bank 500 PSMIOVCCO_PSIO0_5001.8V

Bank 501 PSMIO



Bank 502 PSMIOVCCO_PSIO2_5021.8V
Bank 504 PSDDRDDR_1V21.2V
Zynq SoC bank voltages.

Board to Board Connectors

These connectors are hermaphroditic. Odd pin numbers on the module are connected to even pin numbers on the baseboard and vice versa.

4 x 5 modules use two or three Samtec Razor Beam LSHM connectors on the bottom side.

  • 2 x REF-189016-02 (compatible to LSHM-150-04.0-L-DV-A-S-K-TR), (100 pins, "50" per row)
  • 1 x REF-189017-02 (compatible to LSHM-130-04.0-L-DV-A-S-K-TR), (60 pins, "30" per row) (depending on module)
Connector Mating height

When using the same type on baseboard, the mating height is 8mm. Other mating heights are possible by using connectors with a different height

Order numberConnector on baseboardcompatible toMating height
23836REF-189016-01LSHM-150-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-150-03.0-L-DV-A-S-K-TRLSHM-150-03.0-L-DV-A-S-K-TR7.0 mm
23838REF-189016-02LSHM-150-04.0-L-DV-A-S-K-TR8.0 mm

26125REF-189017-01LSHM-130-02.5-L-DV-A-S-K-TR6.5 mm

LSHM-130-03.0-L-DV-A-S-K-TRLSHM-130-03.0-L-DV-A-S-K-TR7.0 mm
24903 REF-189017-02LSHM-130-04.0-L-DV-A-S-K-TR8.0 mm


The module can be manufactured using other connectors upon request.

Connector Speed Ratings

The LSHM connector speed rating depends on the stacking height; please see the following table:

Stacking heightSpeed rating
12 mm, Single-Ended7.5 GHz / 15 Gbps
12 mm, Differential

6.5 GHz / 13 Gbps

5 mm, Single-Ended11.5 GHz / 23 Gbps
5 mm, Differential7.0 GHz / 14 Gbps
Speed rating.
Current Rating

Current rating of  Samtec Razor Beam™ LSHM B2B connectors is 2.0A per pin (2 adjacent pins powered).

Connector Mechanical Ratings
  • Shock: 100G, 6 ms Sine
  • Vibration: 7.5G random, 2 hours per axis, 3 axes total

Manufacturer Documentation

  File Modified
PDF File hsc-report_lshm-lshm-05mm_web.pdf High speed test report 07 04, 2016 by Thorsten Trenz
PDF File lshm_dv.pdf LSHM catalog page 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-X-DV-A-X-X-TR-FOOTPRINT(1).pdf Recommended layout and stencil drawing 07 04, 2016 by Thorsten Trenz
PDF File LSHM-1XX-XX.X-XX-DV-A-X-X-TR-MKT.pdf Technical drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189016-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-01.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File REF-189017-02.pdf Technical Drawing 07 04, 2016 by Thorsten Trenz
PDF File TC0923--2523_report_Rev_2_qua.pdf Design qualification test report 07 04, 2016 by Thorsten Trenz
PDF File tc0929--2611_qua(1).pdf Shock and vibration report 07 04, 2016 by Thorsten Trenz

Technical Specifications

Absolute Maximum Ratings


VIN supply voltage




See EN6347QI and TPS82085SIL datasheets
3.3VIN supply voltage-0.13.630VXilinx DS925 and TPS27082L datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.630VXilinx document DS925
PS I/O input voltage-0.5VCCO_PSIO + 0.55VXilinx document DS925
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS925
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925
HD I/O bank supply voltage, VCCO-0.53.4VXilinx document DS925
HD I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS925
PS GTR reference clocks absolute input voltage-0.51.1VXilinx document DS925
PS GTR absolute input voltage-0.51.1VXilinx document DS925

Voltage on SC CPLD pins




Lattice Semiconductor MachXO2 datasheet

Storage temperature




See eMMC datasheet
PS absolute maximum ratings

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

ParameterMinMaxUnitsReference Document
VIN supply voltage3.36VSee TPS82085S datasheet
3.3VIN supply voltage3.33.465VSee LCMXO2-256HC, Xilinx DS925 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS925
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS925
HP I/O banks supply voltage, VCCO0.9501.9VXilinx document DS925
HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925
HD I/O banks supply voltage, VCCO1.143.4VXilinx document DS925
HD I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS925
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range085°CXilinx document DS925, extended grade Zynq temperarure range
Recommended operating conditions.

Physical Dimensions

  • Module size: 40 mm × 50 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 8 mm.

PCB thickness: 1.74 mm.

Physical Dimension

Currently Offered Variants 

Trenz shop TE0821 overview page
English pageGerman page
Trenz Electronic Shop Overview

Revision History

Hardware Revision History

DateRevisionChangesDocumentation Link
  • Initial Release
Hardware Revision History

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Board hardware revision number.

Document Change History


Martin Rohrmüller

  • bugfix boot mode

2021-07-05v.61John Hartfiel
  • Update download Link

  • Update Change history
2021-06-07v.59Vadim Yunitski
  • Added missing text in Bank Voltages
  • Fixed typo in Bank Voltages
2020-07-15v.50Pedram Babakhani
  • Initial Release



  • --
Document change history.


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Trenz Electronic GmbH herewith declares that all its products are developed, manufactured and distributed RoHS compliant.


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Users of electrical and electronic equipment in private households are required not to dispose of waste electrical and electronic equipment as unsorted municipal waste and to collect such waste electrical and electronic equipment separately. By the 13 August 2005, Member States shall have ensured that systems are set up allowing final holders and distributors to return waste electrical and electronic equipment at least free of charge. Member States shall ensure the availability and accessibility of the necessary collection facilities. Separate collection is the precondition to ensure specific treatment and recycling of waste electrical and electronic equipment and is necessary to achieve the chosen level of protection of human health and the environment in the European Union. Consumers have to actively contribute to the success of such collection and the return of waste electrical and electronic equipment. Presence of hazardous substances in electrical and electronic equipment results in potential effects on the environment and human health. The symbol consisting of the crossed-out wheeled bin indicates separate collection for waste electrical and electronic equipment.

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