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Test Points

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id	Comments

you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

EEPROM 0x50 -

MIO Pins

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hidden true id Comments
you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic. Example: MIO Pin Connected to B2B Notes MIO12...14 SPI_CS , SPI_DQ0... SPI_DQ3, SPI_SCK J2 QSPI

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anchor Table_SIP_MIOs title MIOs pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin Connected to B2B Notes 0...5 QSPI Flash, U7 - SPI Flash 7...12 QSPI Flash, U17 - SPI Flash 13...23 eMMC, U6 24 ETH Transceiver, U8 - ETH_RST 25 USB2.0 Transceiver, U18 - OTG_RST 26...33 User MIO JM1 34...37 N.C - N.C 38...39 EEPROM, U25 - I2C_SDA/SCL 40...45 N.C N.C 46...51 SD Card JM1 52...63 USB2.0 Transceiver, U18 - 63...77 Ethernet Transceiver, U8 -

Test Points

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hidden true id Comments
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section. Example: Test Point Signal B2B Notes 10 PWR_PL_OK J2-120

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anchor Table_SIP_TPs title Test Points Information
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Test Point Signal Connected to Notes 1 I2C_SCL EEPROM, U25 2 I2C_SDA EEPROM, U25 3 SRST_B FPGA Bank 503 PSCONFIG 4 PS_CLK FPGA Bank 503 PSCONFIG 5 PROG_B FPGA Bank 503 PSCONFIG 6 INIT_B FPGA Bank 503 PSCONFIG 7 DONE Red LED, D1 8 PS_LP0V85 Voltage Regulator, U12 9 DDR_2V5 Voltage Regulator, U4 10 PS_AVCC Voltage Regulator, U9 11 DDR_1V2 Voltage Regulator, U15 12 PS_AVTT Voltage Regulator, U3 13 PS_FP0V85 Voltage Regulator, U26 14 POR_B Voltage Translator, U19 15 PS_PLL Voltage Regulator, U23 16 PL_VCCINT Voltage Regulator, U5

On-board Peripherals

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Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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anchor	Table_SIP_TPs
title	Test Points Information

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On-board Peripherals

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hidden true id Comments
Notes : add subsection for every component which is important for design, for example: Two 100 Mbit Ethernet Transciever PHY USB PHY Programmable Clock Generator Oscillators eMMCs RTC FTDI ... DIP-Switches Buttons LEDs

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Notes : In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor	Table_OBP
title	On board peripherals

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hidden true id Comments
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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anchor Table_OBP_SPI title Quad SPI interface MIOs and pinsOn board peripherals
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Pin Chip/Interface Schematic Designator Notes QSPI Flash U7 Pin , U17 PinnCS EEPROM MIO5 U25	MIO7	CLK	MIO0	MIO12	DI/IO0	MIO4	MIO8	DO/IO1	MIO1	MIO9	nHOLD/IO3	MIO3	MIO11	WP/IO2	MIO2	MIO10

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DDR4 SDRAM U2,U3 GigaBit Ethernet U8 USB2.0 Transceiver U18 eMMC Memory U6 Oscillators U32, U14, U11 Programmable Clock Generator U25 CPLD U21 LEDs D1...3

Quad SPI Flash Memory

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hidden true id Comments
Notes : Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TE0821 is equipped with dual Flash Memory, U7, U17.  Two quad SPI compatible serial bus flash MT25QU512ABB8E12-0SIT memory chips are provided for FPGA configuration file storage. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

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anchor Table_OBP_SPI title Quad SPI interface MIOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Pin Schematic Notes U7 Pin U17 Pin nCS MIO5 MIO7 CLK MIO0 MIO12 DI/IO0 MIO4 MIO8 DO/IO1 MIO1 MIO9 nHOLD/IO3 MIO3 MIO11 WP/IO2 MIO2 MIO10

EEPROM

There is a 2Kb EEPROM provided on the module TE0821.

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anchor Table_OBP_EEP title I2C EEPROM interface MIOs and pins
Scroll Table Layout orientation portrait

There is a 2Kb EEPROM provided on the module TE0821.

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anchor Table_OBP_EEP title I2C EEPROM interface MIOs and pins
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true MIO Pin Schematic U25 Pin Notes MIO39 I2C_SDA SDA MIO38 I2C_SCL SCL

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anchor Table_OBP_LED title On-board LEDs
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Color Connected to Active Level Note D1 Red DONE Low D2 Green USR_LED High D3 Red ERR_OUT High D4 Green USR_LED High D3 Red ERR_OUT High D4 Green ERR_STATUS High

DDR4 SDRAM

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hidden true id Comments
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0821 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

• Part number: K4A8G165WB-BIRC
• Supply voltage: 1.2V
• Speed: 2400 Mbps
• Temperature: -40 ~ 95 °C

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ERR_STATUS High

DDR4 SDRAM

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hidden true id Comments
Notes : Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE0821 SoM has dual 8 Gb volatile DDR4 SDRAM IC for storing user application code and data.

• Part number: K4A8G165WB-BIRC
• Supply voltage: 1.2V
• Speed: 2400 Mbps
• Temperature: -40 ~ 95 °C

System Controller CPLD

The System Controller CPLD (U21) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 product family). It is the central system management unit with module specific firmware installed to monitor and control various signals of the FPGA, on-board peripherals, I/O interfaces and module as a whole.

See also TE0821 System Controller CPLD page. 

GigaBit Ethernet

On-board Gigabit Ethernet PHY (U8) is provided with Marvell Alaska 88E1512 IC (U8). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the PHY is supplied from an on-board 25.00 MHz oscillator (U11).

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anchor Table_OBP_ETH title Ethernet PHY to Zynq SoC connections
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Pin Schematic Connected to Note MDIP0...3 PHY_MDI0...3 B2B, JM1 MDC ETH_MDC MIO76 MDIO ETH_MDIO MIO77 S_IN S_IN B2B, JM3 S_OUT S_OUT B2B, JM3 TXD0..3 ETH_TXD0...3 MIO65...68 TX_CTRL ETH_TXCTL MIO69 TX_CLK ETH_TXCK MIO64 RXD0...3 ETH_RXD0...3 MIO71...74 RX_CTRL ETH_RXCTL MIO75 RX_CLK ETH_RXCK MIO70 LED0...2 PHY_LED0...2 FPGA Bank 66 RESETn ETH_RST MIO24

USB2.0 Transceiver

Hi-speed USB ULPI PHY (U18) is provided with USB3320 from Microchip. The ULPI interface is connected to the Zynq PS USB0 via MIO52..

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63, bank 502. The I/O voltage is fixed at 1.8V and PHY reference clock input is supplied from the on-board 52.00 MHz oscillator (U14).

eMMC Flash Memory

eMMC Flash memory device(U6) is connected to the ZynqMP PS MIO bank 500 pins MIO13..MIO23. eMMC chips IS21ES08G-JCLI (FLASH - NAND Speicher-IC (64 Gb x 1) MMC ) is used.

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Clock Sources

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anchor Table_OBP_CLK title Osillators
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Designator Description Frequency Note U11 MEMS Oscillator 25 MHz U14 MEMS Oscillator 52 MHz U32 MEMS Oscillator 80 MHz

Programmable Clock Generator

Oscillator 80 MHz

Programmable Clock Generator

There is a Silicon Labs I²C programmable clock generator Si5338A (U10) chip on the module. It's output frequencies can be programmed using the I²C bus address 0x70 or 0x71. Default address is 0x70, IN4/I2C_LSB pin must be set to high for address 0x71.

A 25.00 MHz oscillator is connected to the pin IN3 and is used to generate the output clocks. The oscillator has its output enable pin permanently connected to 1.8V power rail, thus making output frequency available as soon as 1.8V is present. Three of the Si5338 clock outputs are connected to the FPGA. One is connected to a logic bank and the other two are connected to the GTR banks.

Once running, the frequency and other parameters can be changed by programming the device using the I²C bus connected between the FPGA (master) and clock generator (slave). For this, proper I²C bus logic has to be implemented in FPGAThere is a programmable clock generator on-board (U10) provided in order to generate variable clocks for the module. Programming can be done using I²C via PIN header J??.  The I²C Address is 0x70 or 0x71.

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anchor Table_OBP_PCLK title Programmable Clock Generator Inputs and Outputs
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default sortByColumn 1 sortEnabled false cellHighlighting true U25 Pin Signal Connected to Direction Note IN0..1 CLK_IN JM3 IN IN2 CLK_25M Oscillator, U11 IN SCL I2C_SCL EEPROM,U25 INOUT SDA I2C_SDA EEPROM,U25 INOUT CLK0 CLK0 JM3 OUT CLK1 B505_CLK3 FPGA Bank 505 IN CLK2 B505_CLK1 FPGA Bank 505 IN CLK3 CLK3_N IN

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Power supply with minimum current capability of xx 3 A for system startup is recommended.

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HP: 1.0V to 1.8V

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anchor Table_PWR_BV title Zynq SoC bank voltages.
Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true sortEnabled false cellHighlighting true FPGA Bank Schematic Voltage Note 24 HD VCCO_HD24_24 Variable  Max voltage 3.3V 25 HD Variable  Max voltage 3.3V 26 HD VCCO_HD25_26 Variable  Max voltage 3.3V 44 HD VCCO_HD24_44 Variable Max voltage 3.3V
Bank	Schematic Name	Voltage	Notes
64 HP	VCCO_64	User

65 HP	VCCO_65

User

Variable

Max voltage

HP: 1.0V to

1.8V
66 HP	VCCO_66

UserHP: 1.0V to

1.8V
500 PSMIO	VCCO_PSIO0_500	1.8V

 -

501 PSMIO	VCCO_PSIO1_501	3.3V

 -

502 PSMIO	VCCO_PSIO2_502	1.8V

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503 PSCONFIG	VCCO_PSIO3_503	1.8V

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504 PSDDR

VCCO

DDR_

PSDDR_504

1V2

1.2V

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