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| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
| PWR_STATUS | out | 36 | 1.8V_CPLD | Output for Status-LED (After successful configuration of FPGA is connected automatically with FPGA_IO0) |
| MODE0 | out | 35 | 1.8V_CPLD | ZynqMP boot mode pin 0 |
| PG_VCCRF | in | 34 | 1.8V_CPLD | Power Good input from PWR_PRE |
| SRST_B | out | 33 | 1.8V_CPLD | FPGA external system reset / currently_not_used |
| PROG_B | out | 32 | 1.8V_CPLD | FPGA reset PL configuration logic / currently_not_used |
| PG_GR2 | in | 31 | 1.8V_CPLD | Power control input from PWR_PS and PWR_DDR |
| MIO28_UART1_TX | out | 29 | 1.8V_CPLD | UART Transmition pin / currently_not_used |
| MIO28_UART1_RX | in | 28 | 1.8V_CPLD | UART Receive pin / currently_not_used |
| FPGA_IO0 | out | 27 | 1.8V_CPLD | FPGA GPIO / User LED |
| FPGA_IO1 | inout | 26 | 1.8V_CPLD | FPGA GPIO / User dip switch interface |
| EN_PS_PL | out | 14 | 3.3V_CPLD | Power enable for PWR_CORE , PWR_PS and PWR_GT |
| EN_GR1 | out | 15 | 3.3V_CPLD | Power enable for PWR_GT and PWR_PS |
| EN_RF_ADC | out | 16 | 3.3V_CPLD | Power enable for PWR_ADC |
| PG_RF_DAC | in | 17 | 3.3V_CPLD | Power control input from PWR_DAC |
| EN_VCCRF | out | 18 | 3.3V_CPLD | Power enable for PWR_PRE |
| EN_GR2 | out | 19 | 3.3V_CPLD | Power enable for PWR_DDR , PWR_GT and PWR_PS |
| PG_PS_PL | in | 20 | 3.3V_CPLD | power control input from PWR_CORE , PWR_GT and PWR_PS |
| PG_GR1 | in | 21 | 3.3V_CPLD | Power control input from PWR_GT and PWR_PS |
| PG_RF_ADC | in | 23 | 3.3V_CPLD | Power control input from PWR_ADC |
| EN_RF_DAC | out | 24 | 3.3V_CPLD | Power enable for PWR_DAC |
| MODE2 | out | 2 | 1.8V_CPLD | ZynqMP boot mode pin 2 |
| MODE1 | out | 3 | 1.8V_CPLD | ZynqMP boot mode pin 1 |
| POR_B | out | 4 | 1.8V_CPLD | Power-On reset signal |
| MODE3 | out | 5 | 1.8V_CPLD | ZynqMP boot mode pin 3 |
| INIT_B | in | 7 | 1.8V_CPLD | FPGA PL initialization activity and configuration error signal / currently_not_used |
| F_TDI | out | 8 | 1.8V_CPLD | JTAG ZynqMP |
| F_TMS | out | 9 | 1.8V_CPLD | JTAG ZynqMP |
| F_TCK | out | 10 | 1.8V_CPLD | JTAG ZynqMP |
| F_TDO | in | 11 | 1.8V_CPLD | JTAG ZynqMP |
| DONE | in | 12 | 1.8V_CPLD | FPGA PL configuration done indicator |
| JTAG_TDO | out | 48 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TDI | in | 47 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TCK | in | 45 | 3.3V_CPLD | JTAG_B2B |
| JTAG_TMS | in | 44 | 3.3V_CPLD | JTAG_B2B |
| CPLD_IO0 | in | 43 | 3.3V_CPLD | BOOT Mode input pin 0 |
| CPLD_IO1 | in | 42 | 3.3V_CPLD | BOOT Mode input pin 1 |
| CPLD_JTAGEN | in | 41 | 3.3V_CPLD | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) |
| CPLD_IO2 | in | 40 | 3.3V_CPLD | CPLD IO to B2B / Used as dip switch interface on the carrier board (After successful configuration of FPGA is connected automatically with FPGA_IO1) |
| CPLD_IO3 | out | 38 | 3.3V_CPLD | CPLD IO to B2B/ Used as power good, can be used to enable carrier periphery power |
| RESETN | in | 37 | 3.3V_CPLD | Reset pin of CPLD (Active low) |
Functional Description
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- FPGA_IO1 (AE16 of RFSoC) is connected with CPLD_IO2 (S1-3 Dip switch on the carrier board) when the FPGA is programmed correctly otherweise this pin is high impedance. After configuration of the FPGA can user use this pin as input.
- FPGA_IO0 (AE18 of RFSOC) is connected with LED on the RFSoC module (D1) if the FPGA is programmed completely otherweise this LED (D1) blinks according to the state of the power-on sequencing. After configuration of the FPGA can be controlled this LED (D1) by user.
If the FPGA correctly programmed (DONE signal is high) and the power-on sequencing state is RDY then the User IOs can be shown in the following table:
| Component | Designator | Pin Name | Pin Number | Board | Interface | Connected in the Hardware with | Designator | Pin Name | Pin Number | Board | after programming the FPGA connected with | Designator | Pin Name | Pin Number | Board |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| Dip Switch | S1-3 | CPLD_IO2 | --- | TEB0835 | B2B | CPLD | U31 | CPLD_IO2 | 40 | TE0835 | FPGA | U1 | FPGA_IO1 | AE16 | TE0835 |
| FPGA | U1 | FPGA_IO0 | AE18 | TE0835 | --- | CPLD | U31 | FPGA_IO0 | 27 | TE0835 | LED | D1 | --- | --- | TE0835 |
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Overview
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