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If the FPGA correctly programmed (DONE signal is high) and the power-on sequencing state is RDY then the User IOs can be shown in the following table:
| Function | Interface | Schematic | FPGA Pin | Note | ||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| USER signal | B2B (J1-32) | |||||||||||||||||||||||
| Component | Designator | Pin Name | Pin Number | Board | Interface | Connected in the Hardware with | Designator | Pin Name | Pin Number | Board | after programming the FPGA connected with | Designator | Pin Name | Pin Number | Board | |||||||||
| Dip Switch | S1-3 | CPLD_IO2 | --- | TEB0835 | B2B | CPLD | U31 | CPLD_IO2 | 40 | TE0835 | FPGA | U1 | FPGA_IO1 | AE16 | TE0835 | FPGA | U1 | FPGA_IO0 | AE18 | TE0835 | --- | CPLD | U31 | source by TEB0835 Dip Switch S1-3, in case FPGA is programmed |
| LED (D1) | -- | FPGA_IO0 | 27AE18 | TE0835 | LED | D1 | --- | --- | TE0835controls LED, in case FPGA is programmed |
Boot Mode
Boot Modes can be selected via B2B Pin Mode.
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Overview
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