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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
20212022-0608-28243.1.8
  • added boot process for Microblaze
  • minor typos, formatting11
    • Modification from link "available short link"
    ma
    20212022-0601-01253.1.7
    • carrier reference note
    jh
    2021-05-043.1.6
    • removed zynq_ from zynq_fsbl
    ma
    2021-04-2810
    • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
    • corrected Boot Source File in Boot Script-File
    ma
    2022-01-143.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • 9
    • extended notes for microblaze boot process with linux
    • add u.boot.dtb to petalinux notes
    • add dtb to prebuilt content
    • replace 20.2 with 21.2
    jh
    2021-06-283.1.8
    • added boot process for Microblaze
    • minor typos, formatting
    ma
    2021-0406-27013.1.4
  • Version History
    • changed from list to table
  • Design flow
  • removed step 5 from Design flow
  • changed link from TE Board Part Files to Vivado Board Part Flow
  • changed cmd shell from picture to codeblock
  • added hidden template for "7
    • carrier reference note
    jh
    2021-05-043.1.6
    • removed zynq_ from zynq_fsbl
    ma
    2021-04-283.1.5
    • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
    • minor typos, formatting
    ma
    2021-04-273.1.4
    • Version History
      • changed from list to table
    • Design flow
      • removed step 5 from Design flow
      • changed link from TE Board Part Files to Vivado Board Part Flow
      • changed cmd shell from picture to codeblock
      • added hidden template for "Copy PetaLinux build image files", depending from hardware
      • added hidden template for "Power on PCB", depending from hardware
    • Usage update of boot process
    • Requirements - Hardware
      • added "*used as reference" for hardware requirements
    • all
      • placed a horizontal separation line under each chapter heading
      • changed title-alignment for tables from left to center
    • all tables
      • added "<project folder>\board_files" in Vivado design sources
    ma

    3.1.3
    • Design Flow
      • formatting
    • Launch
      • formatting
    ma

    3.1.2
    • minor typing corrections
    • replaced SDK by Vitis
    • changed from / to \ for windows paths
    • replaced <design name> by <project folder>
    • added "" for path names
    • added boot.src description
    • added USB for programming
    ma

    3.1.1
    • swapped order from prebuilt files
    • minor typing corrections
    • removed Win OS path length from Design flow, added as caution in Design flow
    ma

    3.1
    • Fix problem with pdf export and side scroll bar
    • update 19.2 to 20.2
    • add prebuilt content option


    3.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator


    Custom_table_size_100

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    Important General Note:

    • Export PDF to download, if vivado revision is changed!

    • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

      • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
        • Figure template (note: inner scroll ignore/only only with drawIO object):

          Scroll Title
          anchorFigure_xyz
          titleText


          Scroll Ignore

          Create DrawIO object here: Attention if you copy from other page, use


          Scroll Only

          image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



        • Table template:

          • Layout macro can be use for landscape of large tables
          • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

        • Scroll Title
          anchorTable_xyz
          titleText

          Scroll Table Layout
          orientationportrait
          sortDirectionASC
          repeatTableHeadersdefault
          style
          widths
          sortByColumn1
          sortEnabledfalse
          cellHighlightingtrue

          ExampleComment
          12



    • ...

    Overview

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    Notes :

    • short description of the design

    • Short Link of "Scroll only" macro:

    Linux with basic periphery of TE0818 StarterKit (TEBF0818 Carrier).

    Refer to http://trenz.org/te0813-info for the current online version of this manual and other available documentation.

    Key Features

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    Notes :

    • Add basic key futures, which can be tested with the design


    Excerpt
    • Vitis/Vivado 20202021.2.1
    • TEBF0818
    • PetaLinux
    • USB
    • ETH
    • MAC from EEPROM
    • PCIe
    • SATA
    • SD
    • I2C
    • RGPIO
    • Display Port (DP)
    • user LED access
    • Modified FSBL for Si5338 programming/ petalinux patch
    • Special FSBL for QSPI Programming

    Revision History

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    Notes :

    • add every update file on the download
    • add design changes on description


    Scroll Title
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    titleDesign Revision History
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    DateVivadoProject BuiltAuthorsDescription
    20212022-10-282020202021.2.1TE0813-StarterKit_noprebuilt-vivado_20202021.2-build_819_2021102814254220221020112739.zip
    TE0813-StarterKit_noprebuilt-vivado_20202021.2-build_819_2021102814261420221020112739.zip
    Manuela Strücker
    • initial Vivado 2021.2.1 release

    Release Notes and Know Issues

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    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if issue fixed
    • new variants
    • script update
    2021-11-162020.2TE0813-StarterKit_noprebuilt-vivado_2020.2-build_9_20211116073800.zip
    TE0813-StarterKit-vivado_2020.2-build_9_20211116073742.zip
    John Hartfiel
    • new variants
    2021-10-282020.2TE0813-StarterKit-vivado_2020.2-build_8_20211028142542.zip
    TE0813-StarterKit_noprebuilt-vivado_2020.2-build_8_20211028142614.zip
    Manuela Strücker
    • initial release


    Release Notes and Know Issues

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    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if issue fixed


    Scroll Title
    anchorTable_KI
    title-alignmentcenter
    titleKnown Issues

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    IssuesDescriptionWorkaround/SolutionTo be fixed version
    QSPI FlashProgramming QSPI flash fails sometimesuse Vivado 2019.2 for Xilinx SoftwareIncompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Requestuse corresponding board files for the Vivado versions--
    QSPI FlashProgramming QSPI flash fails sometimesuse Vivado 2019.2 for programming--


    Requirements

    Software

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    Notes :

    • list of software which was used to generate the design


    Scroll Title
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    titleSoftware

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    SoftwareVersionNote
    Vitis20202021.2.1needed, Vivado is included into Vitis installation
    PetaLinux20202021.2.1needed
    SI ClockBuilder Pro---optional


    Hardware

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    Notes :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *

    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:

    Content

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    Notes :

    • content of the zip file

    For general structure and usage of the reference design, see Project Delivery - Xilinx devices

    Design Sources
    Scroll Title
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    title-alignmentcenter
    titleHardware Modules

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    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0813-01-4BE11-A*4eg_1e_2gbREV012GB128MBNANANA
    TE0813-01-2AE11-A2cg_1e_2gbREV012GB128MBNANANA

    *used as reference

    Note: Design contains also Board Part Files for TE0818 only configuration, this board part files are not used for this reference design.

    Design supports following carriers:

    Scroll Title
    anchorTable_HWC
    title-alignmentcenter
    titleHardware Carrier
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueCarrier ModelNotesTEBF0818*Used as reference carrier.

    *used as reference

    Additional HW Requirements:

    Scroll Title
    anchorTable_AHW
    title-alignmentcenter
    titleAdditional Hardware
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueAdditional HardwareNotesDP Monitor

    Optional HW
    Not all monitors are supported, also Adapter to other Standard can make trouble.
    Design was tested with DELL P2421

    USB KeyboardOptional HW
    Can be used to get access to console which is show on DPUSB StickOptional HW
    USB was tested with USB memory stickSata DiskOptional HWPCIe CardOptional HWETH cableOptional HW
    Ethernet works with DHCP, but can be setup also manuallySD cardwith fat32 partition
    TE0813-01-2BE11-A2eg_1e_2gbREV012GB128MBNANANA
    TE0813-01-3AE11-A3cg_1e_2gbREV012GB128MBNANANA
    TE0813-01-4AE11-A4cg_1e_2gbREV012GB128MBNANANA
    TE0813-01-5DE11-A5ev_1e_2gbREV012GB128MBNANANA
    TE0813-01-3BE11-A3eg_1e_2gbREV012GB128MBNANANA
    TE0813-01-4DE11-A4ev_1e_2gbREV012GB128MBNANANA
    TE0813-01-4DE11-AZ4ev_1e_2gbREV012GB128MBNANANA
    TE0813-01-4BE71-A4eg_1e_4gbREV014GB128MBNANANA
    TE0813-01-4BE11-AZ4eg_1e_2gbREV012GB128MBNANANA

    *used as reference

    Note: Design contains also Board Part Files for TE0818 only configuration, this board part files are not used for this reference design.

    Design supports following carriers:

    Scroll Title
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    title-alignmentcenter
    titleHardware Carrier

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    Carrier ModelNotes
    TEBF0818*Used as reference carrier.

    *used as reference

    Additional HW Requirements:

    Scroll Title
    anchorTable_DSAHW
    title-alignmentcenter
    titleDesign sourcesAdditional Hardware

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    TypeLocationAdditional HardwareNotes
    Vivado<project folder>\block_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\board_files
    Vivado Project will be generated by TE Scripts
    Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
    PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration
    Additional
    DP Monitor

    Optional HW
    Not all monitors are supported, also Adapter to other Standard can make trouble.
    Design was tested with DELL P2421

    USB KeyboardOptional HW
    Can be used to get access to console which is show on DP
    USB StickOptional HW
    USB was tested with USB memory stick
    SATA DiskOptional HW
    PCIe CardOptional HW
    ETH cableOptional HW
    Ethernet works with DHCP, but can be setup also manually
    SD cardwith fat32 partition


    Content

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    Notes :

    • content of the zip file

    For general structure and usage of the reference design, see Project Delivery - Xilinx devices

    Design Sources

    Scroll Title
    anchorTable_ADSDS
    title-alignmentcenter
    titleAdditional design Design sources

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    Notes :

  • prebuilt files
  • Template Table:
    TypeLocationNotes
    SI5338Vivado<project folder>\misc\Si5338SI5338 Project with current PLL Configurationinit.shblock_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\misc\sd
    Additional Initialization Script for Linux

    Prebuilt

    board_filesVivado Project will be generated by TE Scripts
    Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
    PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration



    Additional Sources

    PFPrebuilt files*.mcs
    Scroll Title
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    ADS
    title-alignmentcenter
    title
    Additional design sources

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    File
    Type
    File-Extension
    Location
    Description

    MCS-File

    Notes
    BIF-File*.bifFile with description to generate Bin-FileBIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)BIT-File*.bitFPGA (PL Part) Configuration FileBoot Source*.scr

    Distro Boot file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

    Debian SD-Image

    *.img

    Debian Image for SD-Card

    Diverse Reports---Report files in different formatsHardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinuxLabTools Project-File*.lprVivado Labtools Project File
    SI5338<project folder>\misc\PLL\Si5338_BSI5338 Project with current PLL Configuration
    init.sh<project folder>\misc\sdAdditional Initialization Script for Linux



    Prebuilt

    Image
    • prebuilt files
    • Template Table:

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    Notes :

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    repeatTableHeadersdefault
    stylewidths
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    sortEnabledfalse
    cellHighlightingtrue

    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Source*.scr

    Distro Boot file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ub
    Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files

    Scroll Table Layout
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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (MicroBlaze or FPGA part onlyZynq-FPGAs)
    MMIBIT-File*.mmi

    File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

    SREC-File

    *.srec

    Converted Software Application for MicroBlaze Processor Systems

    Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)
      • bitFPGA (PL Part) Configuration File
        Boot Script-File*.scr

        Distro Boot Script file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
        Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description

    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    Code Block
    languagebash
    themeMidnight
    title_create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> ---------------------------------------
      • SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems





    Scroll Title
    anchorTable_PF
    title-alignmentcenter
    titlePrebuilt files (only on ZIP with prebult content)

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Script-File*.scr

    Distro Boot Script file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

    Page properties
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    Reference Design is available on:

    Design Flow

    Scroll Ignore
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    Page properties
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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
      languagebash
      themeMidnight
      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths-----
      -----------------------
      --TE ReferenceRun Design----- with: _create_win_setup
      -- Use Design Path: <absolute project path>
      -----------------------
      ---------------------------------------------
      -----------------------
      --TE (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Reference Design---------------------------
      --------------------------------------------------------------------
      -- (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Go to CMD-File Generation (Manual setup)
      -- (d)  Go to Documentation (Web Documentation)
      -- (g)  Install Board Files from Xilinx Board Store (beta)
      -- (a)  Start design with unsupported Vivado Version (beta)
      -- (x)  Exit Batch (nothing is done!)
      ----
      Select (ex.:'0' for module selection guide)


    2. Press 0 and enter to start "Module Selection Guide"
    3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note

        Note: Select correct one, see also Vivado Board Part Flow

        • Important: Use Board Part Files, which ends with *_tebf0818


    4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
      • use TE Template from "<project folder>\os\petalinux"
      • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

      • The build images are located in the "<plnx-proj-root>/images/linux" directory

    6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

    7. Copy PetaLinux build image files to prebuilt folder
      • copy u-boot.elf, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

        Info

        "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"


    8. Generate Programming Files with Vitis

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
      TE::sw_run_vitis -all
      TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


      Note

      TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


    Launch

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    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select create and open delivery binary folder

        Info

        Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


    QSPI-Boot mode

    Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

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      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp u-boot
      TE::pr_program_flash -swapp hello_te0813 (optional)
      Note

      To program with Vitis/Vivado GUI, use special FSBL (fsbl_flash) on setup

    3. Copy image.ub and boot.scr on SD or USB
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    4. Set


    5. Set Boot Mode to QSPI-Boot and insert SD or USB.
      • Depends on Carrier, see carrier TRM.
      • TEBF0818 automatically changes the boot mode to SD when the SD card is inserted. Optional CPLD firmware without boot mode change for microSD slot is available in the download area

    SD-Boot mode

    1. Copy image.ub, boot.src and Boot.bin on SD
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

    1. Prepare HW like described on section Programming
    2. Connect UART USB (JTAG XMOD)
    3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

      Info

      Note: See TRM of the Carrier, which is used.


      Tip

      Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
      The boot options described above describe the common boot processes for this hardware; other boot options are possible.
      For more information see Distro Boot with Boot.scr


    4. (Optional) Insert PCIe Card (detection depends on Linux driver. Only some basic drivers are installed)
    5. (Optional) Connect SATA Disc
    6. (Optional) Connect DisplayPort Monitor (List of usable Monitors: https://www.xilinx.com/support/answers/68671.html)
    7. (Optional) Connect Network Cable
    8. Power On PCB

      Expand
      titleboot process

      1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


    Linux

    1. Open Serial Console (e.g. putty)
      • Speed: 115200
      • select COM Port

        Info

        Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


    2. Linux Console:

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      # password default disabled from 2021.2 petalinux release
      petalinux login: root
      Password: root


      Info

      Note: Wait until Linux boot finished


    3. You can use Linux shell now.

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      i2cdetect -y -r 0	(check I2C Bus)
      dmesg | grep rtc	(RTC check)
      udhcpc				(ETH0 check)
      lsusb				(USB check)
      lspci				(PCIe check)


    4. Option Features

      • Webserver to get access to Zynq
        • insert IP on web browser to start web interface
      • init.sh scripts
        • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD")

    Vivado Hardware Manager

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    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only
      • SI5338 CLKs:
        • Set radix from VIO signals to unsigned integer.
          Note: Frequency Counter is inaccurate and displayed unit is Hz
        • expected CLK Frequency...


    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).

    • Control:
      • LEDs: XMOD 2 (without green dot) and HD LED are accessible.
      • CAN_S
    Scroll Title
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    titleVivado Hardware Manager



    System Design - Vivado

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    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

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    titleBlock Design


    PS Interfaces

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    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

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    titlePS Interfaces

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    TypeNote
    DDR
    QSPIMIO
    SD0MIO
    SD1MIO
    CAN0EMIO
    I2C0MIO
    PJTAG0MIO
    UART0MIO
    GPIO0MIO
    SWDT0..1
    TTC0..3
    GEM3MIO
    USB0MIO/GTP
    PCIeMIO/GTP
    SATAGTP
    DisplayPortEMIO/GTP



    Constrains

    Basic module constrains

    Code Block
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    title_i_bitgen.xdc
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

    Design specific constrain

    Code Block
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    title_i_io.xdc
    #TEBF0818 
    # system controller ip
    #LED_HD SC0     J3:C13
    #LED_XMOD SC17  J3:B19 
    #CAN RX SC19 J3   J3:B23 B26_L11L2_P
    #CAN TX SC18    J3:B22 B26_L11L2_N
    #CAN S SC16     J3:B18 B26_L1L3_N
    
    set_property PACKAGE_PIN J14 [get_ports BASE_sc0]
    set_property PACKAGE_PIN F15 [get_ports BASE_sc5]
    set_property PACKAGE_PIN H13 [get_ports BASE_sc6]
    set_property PACKAGE_PIN H14 [get_ports BASE_sc7]
    set_property PACKAGE_PIN A15 [get_ports BASE_sc10_io]
    set_property PACKAGE_PIN B15 [get_ports BASE_sc11]
    set_property PACKAGE_PIN C13 [get_ports BASE_sc12]
    set_property PACKAGE_PIN C14 [get_ports BASE_sc13]
    set_property PACKAGE_PIN E13 [get_ports BASE_sc14]
    set_property PACKAGE_PIN E14 [get_ports BASE_sc15]
    set_property PACKAGE_PIN A13 [get_ports BASE_sc16]
    set_property PACKAGE_PIN B13 [get_ports BASE_sc17]
    set_property PACKAGE_PIN A14 [get_ports BASE_sc18]
    set_property PACKAGE_PIN B14 [get_ports BASE_sc19]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc0]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc5]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc6]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc7]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc10_io]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc11]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc12]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc13]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc14]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc15]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc16]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc17]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc18]
    set_property IOSTANDARD LVCMOS18 [get_ports BASE_sc19]
    
    # Audio Codec
    #LRCLK      J3:D22 
    #BCLK       J3:D23 
    #DAC_SDATA  J3:C21 
    #ADC_SDATA  J3:C22 
    set_property PACKAGE_PIN G14 [get_ports I2S_lrclk ]
    set_property PACKAGE_PIN G15 [get_ports I2S_bclk ]
    set_property PACKAGE_PIN F13 [get_ports I2S_sdin ]
    set_property PACKAGE_PIN G13 [get_ports I2S_sdout ]
    set_property IOSTANDARD LVCMOS18 [get_ports I2S_lrclk ]
    set_property IOSTANDARD LVCMOS18 [get_ports I2S_bclk ]
    set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdin ]
    set_property IOSTANDARD LVCMOS18 [get_ports I2S_sdout ]
    

    Software Design - Vitis

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    Note:
    • optional chapter separate

    • sections for different apps

    For Vitis project creation, follow instructions from:

    Vitis

    Application

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    ----------------------------------------------------------

    FPGA Example

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 20202021.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 20202021.2 xilisf_v5_11

    • Changed default Flash type to 5.

    ----------------------------------------------------------

    Zynq Example:

    fsbl

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    fsbl_flash

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    ZynqMP Example:

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO

    zynqmp_fsbl_flash

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation


    zynqmp_pmufw

    Xilinx default PMU firmware.

    ----------------------------------------------------------

    General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.


    Template location: "<project folder>\sw_lib\sw_apps\"

    zynqmp_fsbl

    TE modified 20202021.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
    • General Changes: 
      • Display FSBL Banner and Device Name


    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • OTG+PCIe Reset over MIO
      • I2C MUX for EEPROM MAC

    zynqmp_fsbl_flash

    TE modified 20192021.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
    • General Changes:
      • Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • Disable Memory initialisation

    zynqmp_pmufw

    Xilinx default PMU firmware.

    hello_te0813

    Hello TE0813 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.


    Software Design -  PetaLinux

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    Note:
    • optional chapter separate

    • sections for linux

    • Add "No changes." or "Activate: and add List"

    For PetaLinux installation and  project creation, follow instructions from:

    Config

    Start with petalinux-config or petalinux-config --get-hw-description

    Activate:

    • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
    • CONFIG_SUBSYSTEM_ETHERNET_PSU_ETHERNET_3_MAC=""

    U-Boot

    Start with petalinux-config -c u-boot
    Changes:

    • CONFIG_I2C_EEPROM=y

    • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA

    • CONFIG_SYS_I2C_EEPROM_ADDR=0x50

    • CONFIG_SYS_I2C_EEPROM_BUS=2

    • CONFIG_SYS_EEPROM_SIZE=256

    • CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0

    • CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0

    • CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1

    • CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0

    • CONFIG_SD_BOOT=y

    Change platform-top.h:

    Code Block
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    Device Tree

    Code Block
    languagejs
    /include/ "system-conf.dtsi" / { chosen { xlnx,eeprom = &eeprom; }; };   /* notes: serdes: https://patchwork.kernel.org/project/linux-arm-kernel/patch/1536769366-31398-2-git-send-email-anurag.kumar.vulisha@xilinx.com/ https://github.com/Xilinx/linux-xlnx/blob/master/include/dt-bindings/phy/phy.h */   /* default */ /* sata */ &sata { phy-names = "sata-phy"; phys = <&lane2 1 0 0 150000000>; //+phys = <PHANDLE CONTROLLER_TYPE CONTROLLER_INSTANCE LANE_REF_CLK LANE_FREQ>; //+ //+PHANDLE = &lane0 or &lane1 or &lane2 or &lane3 //+CONTROLLER_TYPE = PHY_TYPE_PCIE or PHY_TYPE_SATA or PHY_TYPE_USB //+ or PHY_TYPE_DP or PHY_TYPE_SGMII //+CONTROLLER_INSTANCE = Depends on controller type used, can be any of //+ PHY_TYPE_PCIE : 0 or 1 or 2 or 3 //+ PHY_TYPE_SATA : 0 or 1 //+ PHY_TYPE_USB : 0 or 1 //+ PHY_TYPE_DP : 0 or 1 //+ PHY_TYPE_SGMII: 0 or 1 or 2 or 3 //+LANE_REF_CLK
    • ." or "Activate: and add List"

    For PetaLinux installation and  project creation, follow instructions from:

    Config

    Start with petalinux-config or petalinux-config --get-hw-description

    Activate:

    • select SD default instead of eMMC:
      • CONFIG_SUBSYSTEM_PRIMARY_SD_PSU_SD_1_SELECT=y
    • generate u-boot.dtb:
      •  CONFIG_SUBSYSTEM_UBOOT_EXT_DTB=y
    • add new flash partition for bootscr and sizing
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART2_SIZE=0x2000000
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_NAME="bootscr"
      • CONFIG_SUBSYSTEM_FLASH_PSU_QSPI_0_BANKLESS_PART3_SIZE=0x80000

    U-Boot

    Start with petalinux-config -c u-boot
    Changes:

    • MAC from eeprom together with uboot and device tree settings:
      • CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
      • CONFIG_ENV_OVERWRITE=y
      • CONFIG_SYS_I2C_EEPROM_ADDR=0x50
      • CONFIG_SYS_I2C_EEPROM_BUS=7
    • Boot Modes:
      • CONFIG_QSPI_BOOT=y
      • CONFIG_SD_BOOT=y
      • # CONFIG_ENV_IS_IN_NAND is not set
      • CONFIG_BOOT_SCRIPT_OFFSET=0x2A40000


    Change platform-top.h:

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    Device Tree

    Code Block
    languagejs
    titleproject-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi
    /include/ "system-conf.dtsi"
    
    
    /*------------------ gtr --------------------*/
    
    //https://xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
     
    / {
      refclk3:psgtr_dp_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <27000000>;
      };
       
      refclk2:psgtr_pcie_usb_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <100000000>;
      };
    
      refclk1:psgtr_sata_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <150000000>;
      };
    
      refclk0:psgtr_unused_clock {
              compatible = "fixed-clock";
              #clock-cells = <0x00>;
              clock-frequency = <100000000>;
      };
    };
     
    &psgtr {
      clocks = <&refclk0 &refclk1 &refclk2 &refclk3>;
      //clocks = <&refclk0 &refclk2 &refclk3>;
      /* ref clk instances used per lane */
      clock-names = "ref0\0ref1\0ref2\0ref3";
    };
     
     
     
    /*------------------ SD --------------------*/
    &sdhci0 {
        // disable-wp;
        no-1-8-v;
     
    };
     
    &sdhci1 {
        // disable-wp;
        no-1-8-v;
     
    };
     
     
    /*------------------- USB --------------------*/
    &dwc3_0 {
        status = "okay";
        dr_mode = "host";
        snps,usb3_lpm_capable;
        snps,dis_u3_susphy_quirk;
        snps,dis_u2_susphy_quirk;
        phy-names = "usb2-phy","usb3-phy";
        maximum-speed = "super-speed";
    };
    
    
    /*------------------ ETH PHY --------------------*/
    &gem3 {
        phy-handle = <&phy0>;
        
        nvmem-cells = <&eth0_addr>;
        nvmem-cell-names = "mac-address";
        
        phy0: phy0@1 {
            device_type = "ethernet-phy";
            reg = <1>;
        };
    };
     
    
    /*-------------------- QSPI ---------------------*/
    &qspi {
        #address-cells = <1>;
        #size-cells = <0>;
        status = "okay";
        flash0: flash@0 {
            compatible = "jedec,spi-nor";
            reg = <0x0>;
            #address-cells = <1>;
            #size-cells = <1>;
        };
    };
    
    
    /*------------------ I2C --------------------*/
    &i2c0 {
        i2cswitch@73 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x73>;
            i2c-mux-idle-disconnect;
            i2c@0 { // MCLK TEBF0818 SI5338A, 570FBB000290DG_unassembled
                reg = <0>;
            };
            i2c@1 { // SFP TEBF0818 PCF8574DWR
                reg = <1>;
            };
            i2c@2 { // PCIe
                reg = <2>;
            };
            i2c@3 { // SFP1 TEBF0818
                reg = <3>;
            };
            i2c@4 {// SFP2 TEBF0818
                reg = <4>;
            };
            i2c@5 { // TEBF0818 EEPROM
                reg = <5>;
                eeprom: eeprom@50 {
                    compatible = "microchip,24aa025", "atmel,24c02";
                    reg = <0x50>;
                    
                    #address-cells = <1>;
                    #size-cells = <1>;
                    eth0_addr: eth-mac-addr@FA {
                      reg = <0xFA 0x06>;
                    };
               };
            };
            i2c@6 { // TEBF0818 FMC 
                reg = <6>;
            };
            i2c@7 { // TEBF0818 USB HUB
                reg = <7>;
            };
        };
        i2cswitch@77 { // u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
            #size-cells = <0>;
            reg = <0x77>;
            i2c-mux-idle-disconnect;
            i2c@0 { // TEBF0818 PMOD P1
                reg = <0>;
            };
            i2c@1 { // i2c Audio Codec
                reg = <1>;
                /*
                adau1761: adau1761@38 {
                    compatible = "adi,adau1761";
                    reg = <0x38>;
                };
                */
            };
            i2c@2 { // TEBF0818 Firefly A
                reg = <2>;
            };
            i2c@3 { // TEBF0818 Firefly B
                reg = <3>;
            };
            i2c@4 { //Module PLL Si5338 or SI5345
                reg = Depends<4>;
     on which lane clock is used as ref clk, can be
    //+			  0 or 1 or 2 or 3
    //+LANE_FREQ };
            i2c@5 { //TEBF0818 CPLD
                reg  = Frequency<5>;
     of the reference clock, can be any of the
    //+			};
       below mentioned based on the phyi2c@6 type{ used
    //+- PHY_TYPE_PCIETEBF0818 Firefly PCF8574DWR
                reg = 100Mhz
    //+- PHY_TYPE_SGMII<6>;
            = 125Mhz
    //+- PHY_TYPE_SATA};
            i2c@7  = 125Mhz, 150Mhz
    { //+- PHY_TYPE_USB   TEBF0818 PMOD P3
            = 26Mhz, 52Mhz, 100Mhz
    //+- PHY_TYPE_DP   reg = <7>;
            };
     = 27Mhz, 108Mhz, 135Mhz};
     };};


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    titleproject-spec\meta-user\recipes-bsp\uboot-device-tree\files\system-user.dtsi
    /include/ "system-conf.dtsi"
    
    
    /* SD ------------------ gtr --------------------*/
    &sdhci0 {
    	
    //https:// disable-wp;
    	no-1-8-v;
    
    };
    
    &sdhci1 {
    	// disable-wp;
    	no-1-8-v;
    
    };   
    
    /* USB  */
    
    &dwc3_0xilinx-wiki.atlassian.net/wiki/spaces/A/pages/18841716/Zynq+Ultrascale+MPSOC+Linux+SIOU+driver
     
    / {
      refclk3:psgtr_dp_clock {
        status = "okay";
        dr_modecompatible = "hostfixed-clock";
        snps,usb3_lpm_capable;
        snps,dis_u3_susphy_quirk;
        snps,dis_u2_susphy_quirk;
        phy-names = "usb2-phy","usb3-phy"  #clock-cells = <0x00>;
        phys = <&lane1 4 0 2 100000000>;
        maximum-speed clock-frequency = "super-speed"<27000000>;
      };
    
    /* ETH PHY */
    
    &gem3 {
    	phy-handle = <&phy0>;
    	phy0: phy0@1 {
    		device_type
      refclk2:psgtr_pcie_usb_clock {
              compatible = "ethernetfixed-phyclock";
    		reg  = <1>;
    	};
    };
    
    /* QSPI */
    
    &qspi {
        #address#clock-cells = <1><0x00>;
        #size-cells = <0>;
        statusclock-frequency = "okay"<100000000>;
      };
    
      flash0: flash@0refclk1:psgtr_sata_clock {
              compatible = "jedec,spifixed-norclock";
            reg = <0x0>;
            #address #clock-cells = <1><0x00>;
            #size  clock-cellsfrequency = <1><150000000>;
        };
    };
    
    /* I2C */
    
    &i2c0 refclk0:psgtr_unused_clock {
        i2cswitch@73 { // u
            compatible = "nxp,pca9548fixed-clock";
            #address  #clock-cells = <1><0x00>;
              #sizeclock-cellsfrequency = <0><100000000>;
      };
    };
     
    &psgtr {
      clocks = <&refclk0 reg&refclk1 =&refclk2 <0x73>;
      &refclk3>;
      //clocks = <&refclk0  i2c-mux-idle-disconnect&refclk2 &refclk3>;
      /* ref clk instances used per i2c@0lane { *//
     MCLK TEBF0818 SI5338A, 570FBB000290DG_unassembled
                #address-cells = <1>;clock-names = "ref0\0ref1\0ref2\0ref3";
    };
     
     
     
    /*------------------ SD --------------------*/
    &sdhci0 {
        // disable-wp;
           #size-cells = <0>no-1-8-v;
     
    };
     
    &sdhci1 {
        // disable-wp;
         reg = <0>no-1-8-v;
            
    };
     
     
    /*-------------------      i2c@1 { // SFP TEBF0818 PCF8574DWR
      USB --------------------*/
    &dwc3_0 {
        status = "okay";
        dr_mode = "host";
        #address-cells = <1>snps,usb3_lpm_capable;
        snps,dis_u3_susphy_quirk;
        snps,dis_u2_susphy_quirk;
        #sizephy-cellsnames = <0>"usb2-phy","usb3-phy";
        maximum-speed        reg = <1>;= "super-speed";
    };
    
    
    /*------------------ ETH PHY --------------------*/
    &gem3 {
        phy-handle    }= <&phy0>;
            i2c@2 { // PCIe
                #addressnvmem-cells = <1><&eth0_addr>;
                #size-cellsnvmem-cell-names = <0>"mac-address";
        
        phy0: phy0@1   reg{
     = <2>;
          device_type = }"ethernet-phy";
            i2c@3reg { // SFP1 TEBF0818= <1>;
        };
    };
     
    
    /*-------------------- QSPI ---------------------*/
    &qspi {
        #address-cells = <1>;
                #size-cells = <0>;
                reg = <3>status = "okay";
        flash0: flash@0   };{
            i2c@4compatible {// SFP2 TEBF0818= "jedec,spi-nor";
                #address-cells reg = <1><0x0>;
                #size#address-cells = <0><1>;
                reg#size-cells = <4><1>;
            };
    };
    
    
    /*------------------ I2C --------------------*/
    &i2c0 {
        i2cswitch@73 i2c@5 { // TEBF0818 EEPROM
     u
            compatible = "nxp,pca9548";
            #address-cells = <1>;
        
            #size-cells = <0>;
            reg = <0x73>;
       reg    = <5> i2c-mux-idle-disconnect;
            i2c@0 { // MCLK eeprom:TEBF0818 eeprom@50 {
    	SI5338A, 570FBB000290DG_unassembled
                compatiblereg = "atmel,24c08"<0>;
    	        };
            i2c@1 { reg = <0x50>;
    	// SFP TEBF0818 PCF8574DWR
                reg }= <1>;
            };
            i2c@6i2c@2 { // TEBF0818 FMC  PCIe
                #address-cellsreg = <1><2>;
            };
             #size-cells = <0>;i2c@3 { // SFP1 TEBF0818
                reg = <6><3>;
            };
            i2c@7i2c@4 { // SFP2 TEBF0818 USB HUB
                #address-cellsreg = <1><4>;
            };
            i2c@5 { #size-cells = <0>;// TEBF0818 EEPROM
                reg = <7><5>;
            };
         };eeprom: eeprom@50 {
        i2cswitch@77  { // u
            compatible = "nxp,pca9548microchip,24aa025", "atmel,24c02";
            #address-cells = <1>;
          reg  #size-cells = <0><0x50>;
               reg    = <0x77>;
            i2c-mux-idle-disconnect;
            #address-cells i2c@0= {<1>;
     // TEBF0818 PMOD P1
                #address#size-cells = <1>;
                    #size-cells = <0>;
    eth0_addr: eth-mac-addr@FA {
                      reg = <0xFA <0>0x06>;
            };
            i2c@1};
     { // i2c Audio Codec
          };
          #address-cells = <1>};
            i2c@6 { // TEBF0818 #size-cells = <0>;FMC 
                reg = <1><6>;
    			/*
            };
           adau1761: adau1761@38i2c@7 { // TEBF0818 USB HUB
                reg = <7>;
            };
     compatible = "adi,adau1761"  };
        i2cswitch@77 { // u
            compatible reg = <0x38>"nxp,pca9548";
            #address-cells = <1>;
      };
    			*/
          #size-cells = }<0>;
            i2c@2reg { // TEBF0818 Firefly A= <0x77>;
                #address-cells = <1>i2c-mux-idle-disconnect;
            i2c@0 { // TEBF0818 #size-cells = <0>;PMOD P1
                reg = <2><0>;
            };
            i2c@3i2c@1 { // TEBF0818i2c FireflyAudio BCodec
                #address-cellsreg = <1>;
                #size-cells = <0>;/*
                regadau1761: =adau1761@38 <3>;{
            };
            i2c@4compatible { //Module PLL Si5338 or SI5345
    = "adi,adau1761";
                    #address-cellsreg = <1><0x38>;
                #size-cells = <0>};
                reg = <4>;*/
            };
            i2c@5i2c@2 { // TEBF0818 Firefly CPLDA
                #address-cellsreg = <1><2>;
            };
            #size-cells = <0>;i2c@3 { // TEBF0818 Firefly B
                reg = <5><3>;
            };
            i2c@6i2c@4 { //TEBF0818 Firefly PCF8574DWRModule PLL Si5338 or SI5345
                #address-cellsreg = <1><4>;
            };
            i2c@5 #size-cells = <0>;{ //TEBF0818 CPLD
                reg = <6><5>;
            };
            i2c@7i2c@6 { // TEBF0818 PMODFirefly P3PCF8574DWR
                #address-cellsreg = <1><6>;
            };
            i2c@7 { // #size-cellsTEBF0818 =PMOD <0>;P3
                reg = <7>;
            };
        };
    };
    
    

    Kernel

    Start with petalinux-config -c kernel

    Changes:

  • CONFIG_CPU_IDLE is not set (only needed to fix JTAG Debug issue)

  • CONFIG_CPU_FREQ is not set (only needed to fix JTAG Debug issue)

  • CONFIG_NVME_CORE=y
  • CONFIG_BLK_DEV_NVME=y
  • CONFIG_NVME_TARGET=y

    FSBL patch

    currently not included

    Kernel

    Start with petalinux-config -c kernel

    Changes:

    • Only needed to fix JTAG Debug issue:
      • # CONFIG_CPU_IDLE is not set
      • # CONFIG_CPU_FREQ is not set
      • CONFIG_EDAC_CORTEX_ARM64=y
    • Support PCIe memory card
      • CONFIG_NVME_CORE=y
      • CONFIG_BLK_DEV_NVME=y
      • # CONFIG_NVME_MULTIPATH is not set
      • # CONFIG_NVME_HWMON is not set
      • # CONFIG_NVME_TCP is not set
      • CONFIG_NVME_TARGET=y
      • # CONFIG_NVME_TARGET_PASSTHRU is not set
      • # CONFIG_NVME_TARGET_LOOP is not set
      • # CONFIG_NVME_TARGET_FC is not set
      • # CONFIG_NVME_TARGET_TCP is not set
      • CONFIG_SATA_AHCI=y
      • CONFIG_SATA_MOBILE_LPM_POLICY=0
      CONFIG_NVM=y
      • CONFIG_NVM
      _PBLK
      • =y
      • CONFIG_NVM_PBLK
      _DEBUG
      • =y
      • CONFIG_
      EDAC
      • NVM_
      CORTEX
      • PBLK_
      ARM64
      • DEBUG=y

    Rootfs

    Start with petalinux-config -c rootfs

    Changes:

    • For web server app:
      • CONFIG_
      i2c
      • busybox-
      tools
      • httpd=y
    • For additional test tools only:
      • CONFIG_
      busybox
      • i2c-
      httpd
      • tools=y
      (for web server app)
      • CONFIG_packagegroup-petalinux-utils=
      y
      • y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)

    Applications

    See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

    startup

    Script App to load init.sh from SD Card if available.

    webfwu

    Webserver application suitable for Zynq ZynqMP access. Need busybox-httpd

    Additional Software

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    Note:
    • Add description for other Software, for example SI CLK Builder ...
    • SI5338 and SI5345 also Link to:

    SI5338

    File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"

    General documentation how you work with this project will be available on Si5338

    Appx. A: Change History and Legal Notices

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    Document Change History

    To get content of older revision go to "Change History" of this page and select older document revision number.

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    • Release Vivado 2021.2.1
    • new variants
    • script update
    2022-09-06v.4Manuela Strücker
    • new variants
    2021-10-28v.2Manuela Strücker
    • Release 2020.2

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    IN:Legal Notices
    IN:Legal Notices






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