Page History
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| Name / opt. VHD Name | Direction | Pin | Bank Power | Description |
|---|---|---|---|---|
BASE_BTN1 | in | C9 | 3.3V | User button "USER_BTN1" from carrier board TEIB0006 (B2B connector → J2-152) |
| BASE_BTN2 | in | B3 | 3.3V | User button "USER_BTN2" from carrier board TEIB0006 (B2B connector → J2-154) |
| BASE_LED1 | out | A6 | 3.3V | Led "LED1" from carrier board TEIB0006 (B2B connector → J2-146) |
| BASE_LED2 | out | A3 | 3.3V | Led "LED2" from carrier board TEIB0006 (B2B connector → J2-148) |
| DATA0 | in | N5 | 1.8VIO | Data input signal from Intel Cyclone 10 GX |
| DEVCLRN | out | J5 | 1.8VIO | Device-wide reset, Intel Cyclone 10 GX |
| DIS_GROUP1 | out | K12 | 3.3V | Fast Discharging |
| DIS_GROUP2 | out | K10 | 3.3V | Fast Discharging |
| DIS_GROUP3 | out | J9 | 3.3V | Fast Discharging |
| DIS_GROUP4 | out | J12 | 3.3V | Fast Discharging |
| EN_0V9 | out | E9 | 3.3V | Power enable signal 0.9V |
| EN_0V95 | out | J10 | 3.3V | Power enable signal 0.95V |
| EN_1V8 | out | D9 | 3.3V | Power enable signal 1.8V |
| EN_1V8MB | out | H9 | 3.3V | Power enable signal 1.8V for carrier board TEIB0006 (B2B connector → J2-86) |
| EN_1V8VIO | out | L12 | 3.3V | Power enable signal 1.8VIO |
| EN_1V35 | out | D12 | 3.3V | Power enable signal 1.35V |
| EN_3V3MB | out | A11 | 3.3V | Power enable signal 3.3V for carrier board TEIB0006 (B2B connector → J2-74) |
| EN_VTT | out | C11 | 3.3V | Power enable signal VTT |
| F_TCK_OUT | out | N2 | 1.8VIO | JTAG, Intel Cyclone 10 GX |
| F_TDI_OUT | out | M2 | 1.8VIO | JTAG, Intel Cyclone 10 GX |
| F_TDO_IN | in | M3 | 1.8VIO | JTAG, Intel Cyclone 10 GX |
| F_TMS_OUT | out | K1 | 1.8VIO | JTAG, Intel Cyclone 10 GX |
| I2C_SCL | bidir | K2 | 1.8VIO | Clock signal for I2C interface |
| I2C_SDA | bidir | L2 | 1.8VIO | Data signal for I2C interface |
| LED_FP_1 | out | B13 | 3.3V | red led D1, status led for Intel Cyclone 10 GX |
| LED_FP_2 | out | B11 | 3.3V | green led D2, status led for power sequencer core |
| LED_FP_3 | out | A12 | 3.3V | user defined, green led D3 |
| LED_FP_4 | out | B12 | 3.3V | user defined, green led D4 |
| MSEL0 | out | M7 | 1.8VIO | configuration mode selection, Intel Cyclone 10 GX |
| MSEL1 | out | M9 | 1.8VIO | configuration mode selection, Intel Cyclone 10 GX |
| NCONFIG | out | M8 | 1.8VIO | FPGA configuration pin, Intel Cyclone 10 GX |
| NSTATUS | in | M5 | 1.8VIO | FPGA configuration pin, Intel Cyclone 10 GX |
| PG_0V9 | in | E10 | 3.3V | Power Good signal 0.9V, U4 |
| PG_0V95 | in | H10 | 3.3V | Power Good signal 0.95V, U7 |
| PG_1V8 | in | F8 | 3.3V | Power Good signal 1.8V, U5 |
| PG_1V8VIO | in | K11 | 3.3V | Power Good signal 1.8VIO, U6 |
| PG_1V35 | in | E12 | 3.3V | Power Good signal 1.35V, U8 |
| PG_VTT | in | D11 | 3.3V | Power Good signal VTT_DDR, U9 |
| PHY1_33LED1 | out | F10 | 3.3V | green led from RJ45-connector on carrier board TEIB0006 (B2B connector → J2-67) |
| PHY1_33LED2 | out | F9 | 3.3V | yellow led from RJ45-connector on carrier board TEIB0006 (B2B connector → J2-69) |
| PHY1_LED1 | in | J1 | 1.8VIO | led output pin from ethernet phy U2 for PHY1_33LED1 |
| PHY1_LED2 | in | H5 | 1.8VIO | led output pin from ethernet phy U2 for PHY1_33LED2 |
| PLL_RST | out | L3 | 1.8VIO | Device reset for porgrammable oscillator SI5345A, U14 |
| TCK_IN | in | G2 | 3.3V | JTAG, B2B connector → J2-157 |
| TDI_IN | in | F5 | 3.3V | JTAG, B2B connector → J2-159 |
| TDO_OUT | out | F6 | 3.3V | JTAG, B2B connector → J2-158 |
| TMS_IN | in | G1 | 3.3V | JTAG, B2B connector → J2-160 |
| UART_RXD_IN | in | N6 | 1.8VIO | UART, Intel Cyclone 10 GX |
| UART_RXD_OUT | out | A10 | 3.3V | UART, B2B connector → J2-151 |
| UART_TXD_IN | in | B10 | 3.3V | UART, B2B connector → J2-153 |
| UART_TXD_OUT | out | K5 | 1.8VIO | UART, Intel Cyclone 10 GX |
| VADJ_EN | out | C12 | 3.3V | Output enable signal for voltage regulator U11 |
| VADJ_VS0 | out | F12 | 3.3V | Voltage selection signal for voltage regulator U11 |
| VADJ_VS1 | out | E13 | 3.3V | Voltage selection signal for voltage regulator U11 |
| VADJ_VS2 | out | F13 | 3.3V | Voltage selection signal for voltage regulator U11 |
| M10_CLK | in | G9 | 3.3V | Clock input signal, 25 MHz |
Note: Other pins of system controller Intel MAX 10 (U18) are currently not used.
Functional Description
JTAG
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UART signals are routed directly from B2B connector through Intel MAX 10 to Intel Cyclone 10 GX.
LED
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and user buttons
BASE_LED1 (B2B connector → J2-146) and the NCONFIG Pin from Intel Cyclone 10 GX are connected to user button BASE_BTN1 (B2B connector → J2-152).
BASE_LED2 (B2B connector → J2-148) is connected to user button BASE_BTN2 (B2B connector → J2-154).
BASE_BTN2 is also connected to vin_fault input of power sequencer. Vin_fault indicates an external fault, the design sequences all power regulators down, when asserted.
LED_FP_1 is connected to NSTATUS pin from Intel Cyclone 10 GX.
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PHY1_LED1 is directly connected with to PHY1_33LED1.
PHY1_LED2 is directly connected with to PHY1_33LED2.
Power
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All power regulators are controlled by the power sequencer core. It enables and discharges the power regulators and monitors the power good signals.
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The volatile memory of the programmable Oscillator SI5345A is configured via I2C interface with following clock frequencies.
| PLL out | Frequency | I/O Standard |
|---|---|---|
| OUT0 | 100 MHz | LVDS |
| OUT1 | 100 MHz | LVDS |
| OUT2 | 100 MHz | LVCMOS |
| OUT3 | unused | -- |
| OUT4 | unused | -- |
| OUT5 | 200 MHz | LVDS |
| OUT6 | 100 MHz | LVDS |
| OUT7 | 125 MHz | LVDS |
| OUT8 | 100 MHz | LVDS |
| OUT9 | 125 MHz | LVDS |
Appx. A: Change History and Legal Notices
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Overview
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