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Xilinx Zynq-7000 PS has two USB IP Cores that can be used over dedicated MIO pins only (EMIO multiplexing is not supported). If both USB IP Cores is used then SD Card boot is no longer supported.

 

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PHY Reset requirements

Xilinx default standard FSBL can perform USB ULPI PHY Reset only if the reset is directly connected to MIO GPIO, if not then fsbl_hooks.c has to include custom code to reset the USB PHY.

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