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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


2022082411Modification from link "available short link"20220125102022-01-149
  • extended notes for microblaze boot process with linux
  • add u. to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
  • 2021-06-2882021-06-0172021-05-046removed zynq_ from zynq_fsbl2021042852021-04-274
    DateVersionChangesAuthor
    2023-12-143.1.17
    • updated according to Vivado 2023.2
    ma
    2023-06-133.1.
    • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
    • corrected Boot Source File in Boot Script-File
    ma16
    • Design flow:
      • added alternative programming files in Petalinux
    • added chapter FSBL Patch in Software Design - Petalinux
    ma
    2023-06-013.1.15
    • removed u-
    • boot.dtb
    jh
    • from Design flow
    ma
    2023-06-013.1.14
    • expandable lists for revision history and supported hardware
    wh
    2023-05-253.1.
    • added boot process for Microblaze
    • minor typos, formatting
    ma13
    • updated according to Vivado 2022.2
    ma
    2023-02-083.1.
    • carrier reference note
    jh12
    • removed content of
      • Special FSBL for QSPI programming
    ma
    2022-08-243.1.11
    • Modification from link "available short link"
    ma
    2022-01-253.1.
    • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
    • minor typos, formatting
    ma10
    • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
    • corrected Boot Source File in Boot Script-File
    ma
    2022-01-143.1.
    • Version History
      • changed from list to table
    • Design flow
      • removed step 5 from Design flow
      • changed link from TE Board Part Files to Vivado Board Part Flow
      • changed cmd shell from picture to codeblock
      • added hidden template for "Copy PetaLinux build image files", depending from hardware
      • added hidden template for "Power on PCB", depending from hardware
    • Usage update of boot process
    • Requirements - Hardware
      • added "*used as reference" for hardware requirements
    • all
      • placed a horizontal separation line under each chapter heading
      • changed title-alignment for tables from left to center
    • all tables
      • added "<project folder>\board_files" in Vivado design sources
    ma3.1.3
    • Design Flow
      • formatting
    • Launch
      • formatting
    ma3.1.2
    • minor typing corrections
    • replaced SDK by Vitis
    • changed from / to \ for windows paths
    • replaced <design name> by <project folder>
    • added "" for path names
    • added boot.scr description
    • added USB for programming
    ma3.1.1
    • swapped order from prebuilt files
    • minor typing corrections
    • removed Win OS path length from Design flow, added as caution in Design flow
    ma3.1
    • Fix problem with pdf export and side scroll bar
    • update 19.2 to 20.2
    • add prebuilt content option
    3.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator

    Custom_table_size_100

    9
    • extended notes for microblaze boot process with linux
    • add u.boot.dtb to petalinux notes
    • add dtb to prebuilt content
    • replace 20.2 with 21.2
    jh
    2021-06-283.1.8
    • added boot process for Microblaze
    • minor typos, formatting
    ma
    2021-06-013.1.7
    • carrier reference note
    jh
    2021-05-043.1.6
    • removed zynq_ from zynq_fsbl
    ma
    2021-04-283.1.5
    • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
    • minor typos, formatting
    ma
    2021-04-273.1.4
    • Version History
      • changed from list to table
    • Design flow
      • removed step 5 from Design flow
      • changed link from TE Board Part Files to Vivado Board Part Flow
      • changed cmd shell from picture to codeblock
      • added hidden template for "Copy PetaLinux build image files", depending from hardware
      • added hidden template for "Power on PCB", depending from hardware
    • Usage update of boot process
    • Requirements - Hardware
      • added "*used as reference" for hardware requirements
    • all
      • placed a horizontal separation line under each chapter heading
      • changed title-alignment for tables from left to center
    • all tables
      • added "<project folder>\board_files" in Vivado design sources
    ma

    3.1.3
    • Design Flow
      • formatting
    • Launch
      • formatting
    ma

    3.1.2
    • minor typing corrections
    • replaced SDK by Vitis
    • changed from / to \ for windows paths
    • replaced <design name> by <project folder>
    • added "" for path names
    • added boot.scr description
    • added USB for programming
    ma

    3.1.1
    • swapped order from prebuilt files
    • minor typing corrections
    • removed Win OS path length from Design flow, added as caution in Design flow
    ma

    3.1
    • Fix problem with pdf export and side scroll bar
    • update 19.2 to 20.2
    • add prebuilt content option


    3.0
    • add fix table of content
    • add table size as macro
    • removed page initial creator


    Custom_table_size_100

    Page properties
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    Important General Note:

    • Export PDF to download, if vivado revision is changed!

    • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

      • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
        • Figure template (note: inner scroll ignore/only only with drawIO object):

          Scroll Title
          anchorFigure
    Page properties
    hiddentrue
    idComments

    Important General Note:

    • Export PDF to download, if vivado revision is changed!

    • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

      • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

          Figure template (note: inner scroll ignore/only only with drawIO object):

    Scroll Title
    anchorFigure_xyz
    titleText
    Scroll Ignore

    Create DrawIO object here: Attention if you copy from other page, use

    Scroll Only

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

  • Table template:

    • Layout macro can be use for landscape of large tables
    • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)
  • Scroll Title
    anchorTable_xyz
    titleText


    scroll-ignore

    Create DrawIO object here: Attention if you copy from other page, use


    Scroll Only

    image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



  • Table template:

    • Layout macro can be use for landscape of large tables
    • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

  • Scroll Title
    anchorTable_xyz
    titleText

    tablelayout
    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    ExampleComment
    12



  • ...
  • Overview

    Scroll Ignore
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    scroll-officetrue
    scroll-chmtrue
    scroll-docbooktrue
    scroll-eclipsehelptrue
    scroll-epubtrue
    scroll-htmltrue


    Page properties
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    Notes :

    Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.

    Refer to http://trenz.org/te0745-info for the current online version of this manual and other available documentation.

    Key Features

    Page properties
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    Notes :

    • Add basic key features, which can be tested with the design

    Excerpt
    • Vitis/Vivado 20212023.2.1
    • PetaLinux
    • SD
    • ETH (MAC from EEPROM)
    • USB
    • I2C
    • RTC
    • FMeter
    • Modified FSBL for SI5338 programming

    Revision History

    Page properties
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    Notes :

    • add every update file on the download
    • add design changes on description
    Expandscroll-
    titleExpand List
    Scroll Title
    anchorTable_DRH
    title-alignmentcenter
    titleDesign Revision History

    Scroll Table Layout
    orientationportrait
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    cellHighlightingtrue

    DateVivadoProject BuiltAuthorsDescription
    2024-02-202023.2TE0745-test_board-vivado_2023.2-build_4_20240220094718.zip
    TE0745-test_board_noprebuilt-vivado_2023.2-build_4_20240220094718.zip
    Manuela Strücker
    • update 2023.2
    • new assembly variants
    2023-04-252021.2.1TE0745-test_board-vivado_2021.2-build_20_20230425125003.zip
    TE0745-test_board_noprebuilt-vivado_2021.2-build_20_20230425125003.zip
    Manuela Strücker
    • new assembly variants
    2023-02-072021.2.1TE0745-test_board-vivado_2021.2-build_20_20230207205537.zip
    TE0745-test_board_noprebuilt-vivado_2021.2-build_20
    _20230207205537.zip
    TE0745-test_board_noprebuilt-vivado_2021.2-build_20_20230207205537.zip
    Manuela Strücker
    • update 2021.2
    • new assembly variants
    • added jtag2axi for test purposes
    2020-03-302019.2TE0745-test_board-vivado_2019.2-build_8_20200330083452.zip
    TE0745-test_board_noprebuilt-vivado_2019.2-build_8_20200330083503.zip
    John Hartfiel
    • 2019.2 update
    • FSBL rework, SI5338 Project with Clock Builder pro
    • device tree update
    • Vitis support
    • new assembly variants
    2018-09-20192018.2TE0745-test_board_noprebuilt-vivado_2018.2-build_04_20190918103545.zip
    TE0745-test_board-vivado_2018.2-build_04_20190918103531.zip
    John Hartfiel
    • BUGFIX in TE0745-02-45-3EA board parts
    2018-11-262018.2

    TE0745-test_board-vivado_2018.2-build_03_20181126115131.zip
    TE0745-test_board_noprebuilt-vivado_2018.2-build_03_20181126115320.zip

    John Hartfiel
    • Rework Board Part Files
    • New assembly versions
    • Rework BD Design
    • add init.sh scripts
    2017-10-232017.2TE0745-test_board_noprebuilt-vivado_2017.2-build_05_20171023171903.zip
    TE0745-test_board-vivado_2017.2-build_05_20171023171855.zip
    John Hartfiel
    • initial release
    Release Notes and Know Issues
    _20230207205537.zipManuela Strücker
    • update 2021.2
    • new assembly variants
    • added jtag2axi for test purposes
    2020-03-302019.2TE0745-test_board-vivado_2019.2-build_8_20200330083452.zip
    TE0745-test_board_noprebuilt-vivado_2019.2-build_8_20200330083503.zip
    John Hartfiel
    • 2019.2 update
    • FSBL rework, SI5338 Project with Clock Builder pro
    • device tree update
    • Vitis support
    • new assembly variants
    2018-09-20192018.2TE0745-test_board_noprebuilt-vivado_2018.2-build_04_20190918103545.zip
    TE0745-test_board-vivado_2018.2-build_04_20190918103531.zip
    John Hartfiel
    • BUGFIX in TE0745-02-45-3EA board parts
    2018-11-262018.2

    TE0745-test_board-vivado_2018.2-build_03_20181126115131.zip
    TE0745-test_board_noprebuilt-vivado_2018.2-build_03_20181126115320.zip

    John Hartfiel
    • Rework Board Part Files
    • New assembly versions
    • Rework BD Design
    • add init.sh scripts
    2017-10-232017.2TE0745-test_board_noprebuilt-vivado_2017.2-build_05_20171023171903.zip
    TE0745-test_board-vivado_2017.2-build_05_20171023171855.zip
    John Hartfiel
    • initial release



    Release Notes and Know Issues

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    Notes :
    • add known Design issues and general notes for the current revision
    • do not delete known issue, add fixed version time stamp if  issue fixed


    Scroll Title
    anchorTable_KI
    title-alignmentcenter
    titleKnown Issues

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
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    cellHighlightingtrue

    IssuesDescriptionWorkaroundTo be fixed version
    QSPI programmingQSPI programming is not possible in other boot modes than JTAG.
    • use JTAG boot mode for QSPI programming
    • When using the carrier board TEB0745, use the optional firmware to get into JTAG boot mode.
    ---


    Requirements

    Software

    Page properties
    hiddentrue
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    Notes :

    • list of software which was used to generate the design


    Scroll Title
    anchorTable_SW
    title-alignmentcenter
    titleSoftware

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    SoftwareVersionNote
    Vitis2023.2needed, Vivado is included into Vitis installation
    PetaLinux2023.2needed
    SI ClockBuilder Pro---optional


    Hardware

    Page properties
    hiddentrue
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    Notes

    :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed

    :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *

    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:


    KIKnown Issues
    Expand
    titleExpand List
    Scroll Title
    anchorTable_
    HWM
    title-alignmentcenter
    title
    Hardware Modules

    Scroll Table Layout
    orientationportrait
    sortDirectionASC
    repeatTableHeadersdefault
    style
    widths
    sortByColumn1
    sortEnabledfalse
    cellHighlightingtrue

    IssuesDescriptionWorkaroundTo be fixed version
    QSPI programmingQSPI programming is not possible in other boot modes than JTAG.
    • use JTAG boot mode for QSPI programming
    • When using the carrier board TEB0745, use the optional firmware to get into JTAG boot mode.
    ---

    Requirements

    Software

    Page properties
    hiddentrue
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    Notes :

    • list of software which was used to generate the design
    Scroll Title
    anchorTable_SW
    title-alignmentcenter
    titleSoftware
    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0745-02-30-1I30_1i_1gbREV02|REV011GB32MBNANAless MGT
    TE0745-02-30-2IA30_2i_1gbREV02|REV011GB32MBNANAless MGT
    TE0745-02-35-1C35_1c_1gbREV02|REV011GB32MBNANANA
    TE0745-02-45-1C45_1c_1gbREV02|REV011GB32MBNANANA
    TE0745-02-45-1CA45_1c_1gbREV02|REV011GB64MBNANANA
    TE0745-02-45-2I45_2i_1gbREV02|REV011GB32MBNANANA
    TE0745-02-45-2IA45_2i_1gbREV02|REV011GB64MBNANANA
    TE0745-02-45-3EA45_3e_1gbREV02|REV011GB64MBNANANA
    TE0745-02-71I11-A30_1i_1gbREV021GB64MBNANAless MGT
    TE0745-02-71I11-AK30_1i_1gbREV021GB64MBNANAless MGT
    TE0745-02-71I31-A30_1i_1gbREV021GB64MBNANAless MGT
    TE0745-02-71I31-AK30_1i_1gbREV021GB64MBNANAless MGT
    TE0745-02-71I31-AZ30_1i_1gbREV021GB64MBNANAless MGT
    TE0745-02-72I11-A30_2i_1gbREV021GB64MBNANAless MGT
    TE0745-02-72I31-A30_2i_1gbREV021GB64MBNANAless MGT
    TE0745-02-72I31-AZ30_2i_1gbREV021GB64MBNANAless MGT
    TE0745-02-81C11-A35_1c_1gbREV021GB64MBNANANA
    TE0745-02-81C31-A35_1c_1gbREV021GB64MBNANANA
    TE0745-02-81C31-AZ35_1c_1gbREV021GB64MBNANANA
    TE0745-02-82I31-A35_2i_1gbREV021GB64MBNANANA
    TE0745-02-91C11-A45_1c_1gbREV021GB64MBNANANA
    TE0745-02-91C31-A45_1c_1gbREV021GB64MBNANANA
    TE0745-02-91C31-AZ45_1c_1gbREV021GB64MBNANANA
    TE0745-02-92I11-A45_2i_1gbREV021GB64MBNANANA
    TE0745-02-92I11-F45_2i_ff_1gbREV021GB64MBNANANA
    TE0745-02-92I31-A45_2i_1gbREV021GB64MBNANANA
    TE0745-02-92I31-AK45_2i_1gbREV021GB64MBNANANA
    TE0745-02-92I31-AZ45_2i_1gbREV021GB64MBNANANA
    TE0745-02-92I31-B45_2i_1gbREV021GB64MBNANANA
    TE0745-02-93E11-A45_3e_1gbREV021GB64MBNANANA
    TE0745-02-93E11-KA45_3e_1gbREV021GB64MBNANANA
    TE0745-02-93E31-A45_3e_1gbREV021GB64MBNANANA
    TE0745-02-93E31-AK45_3e_1gbREV021GB64MBNANANA
    TE0745-02-93E31-AZ45_3e_1gbREV021GB64MBNANANA
    TE0745-02-S00345_2i_1gbREV021GB64MBNANAC
    TE0745-02-S00530_1i_1gbREV021GB64MBNANAC;less MGT
    TE0745-02-S00630_1i_1gbREV021GB64MBNAwithout RTCC;less MGT
    TE0745-02-S007C145_2i_1gbREV021GB64MBNAwithout PLLCF
    TE0745-02-S007C245_2i_1gbREV021GB64MBNAwithout PLLCF
    TE0745-02-S007C345_2i_1gbREV021GB64MBNAwithout PLLCF
    TE0745-02-S00830_1i_1gbREV021GB64MBNANAC;less MGT
    TE0745-02-S00930_1i_1gbREV021GB64MBNANAC;less MGT
    TE0745-02-S01245_2i_1gbREV021GB64MBNAwithout PLLC
    TE0745-02-S01345_2i_1gbREV021GB64MBNAwithout PLLC
    TE0745-02-S014C145_2i_1gbREV021GB64MBNAwithout PLLC
    TE0745-02-S014C245_2i_1gbREV021GB64MBNAwithout PLLC
    TE0745-02-S014C345_2i_1gbREV021GB64MBNAwithout PLLC
    TE0745-02-S01645_3e_1gbREV021GB64MBNANAC
    TE0745-02-S01730_1i_1gbREV021GB64MBNANAC;less MGT
    TE0745-02-S01830_1i_1gbREV021GB64MBNANAC;less MGT
    TE0745-02-S01945_2i_1gbREV021GB64MBNANAC
    TE0745-02-S02045_2i_1gbREV021GB64MBNANAC
    TE0745-02-S02145_2i_1gbREV021GB64MBNANAC
    TE0745-02-S02245_2i_1gbREV021GB64MBNANAC
    TE0745-02-S02445_2i_1gbREV021GB64MBNANAC
    TE0745-03-71I31-A30_1i_1gbREV03
    Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueSoftwareVersionNoteVitis2021.2.1needed, Vivado is included into Vitis installationPetaLinux2021.2neededSI ClockBuilder Pro---optional

    Hardware

    Page properties
    hiddentrue
    idComments

    Notes :

    • list of hardware which was used to generate the design
    • mark the module and carrier board, which was used tested with an *

    Basic description of TE Board Part Files is available on TE Board Part Files.

    Complete List is available on "<project folder>\board_files\*_board_files.csv"

    Design supports following modules:

    REV02
    Scroll Title
    anchorTable_HWM
    title-alignmentcenter
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    Scroll Table Layout
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    Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
    TE0745-02-30-1I    30_1i_1gb    REV02|REV01   1GB      32MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-30-2IA   30_2i_1gb    REV02|REV01   1GB      32MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-35-1C    35_1c_1gb    REV02|REV01   1GB      32MB       NA         NA         TE0745-02-45-2I    45_2i_1gb    REV02|REV01   1GB      32MB       NA         NA         TE0745-02-45-2IA   45_2i_1gb    REV02|REV01   1GB      64MB       NA         NA         TE0745-02-45-1C*    45_1c_1gb    REV02|REV01   1GB      32MB       NA         NA         TE0745-02-45-1CA   45_1c_1gb    REV02|REV01   1GB      64MB       NA         NA         TE0745-02-45-3EA   45_3e_1gb    REV02|REV01   1GB      64MB       NA         NA         TE0745-02-93E11-A  45_3e_1gb    REV02         1GB      64MB       NA         NA         TE0745-02-92I11-F  45_2i_ff_1gb REV02         1GB      64MB       NA         NA         TE0745-02-92I11-A  45_2i_1gb    REV02         1GB      64MB       NA         NA         TE0745-02-91C11-A  45_1c_1gb    REV02         1GB      64MB       NA         NA         TE0745-02-81C11-A  35_1c_1gb    REV02         1GB      64MB       NA         NA         
    TE0745-02-72I11-A  30_2i_1gb    REV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-71I11-A  30_1i_1gb    REV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-71I11-AK 30_1i_1gb    REV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs

    TE0745-02-71I31-A 

    30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs

    TE0745-02-71I31-AK

    30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs

    TE0745-02-72I31-A 

    30_2i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs

    TE0745-02-81C31-A 

    35_1c_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-91C31-A 

    45_1c_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-92I31-A 

    45_2i_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-92I31-AK

    45_2i_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-92I31-B 

    45_2i_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-93E11-KA

    45_3e_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-93E31-A 

    45_3e_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-93E31-AK

    45_3e_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-S003    

    45_2i_1gbREV02         1GB      64MB       NA         NA         

    TE0745-02-S005    

    30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs

    TE0745-02-S006

    30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
    without RTC
    TE0745-02-S007C145_2i_1gbREV02         1GB      64MB       NA         NA         without PLL
    TE0745-02-S007C2 45_2i_1gbREV02         1GB      64MB       NA         NA         without PLL
    TE0745-02-S007C345_2i_1gbREV02         1GB      64MB       NA         NA         without PLL
    TE0745-02-S012 45_2i_1gbREV02         1GB      64MB       NA         NA         without PLL
    TE0745-02-S00830_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-S009 30_1i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-82I31-A35_2i_1gbREV02         1GB      64MB       NA         NA         
    TE0745-02-72I31-AZ30_2i_1gbREV02         1GB      64MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-S01345_2i_1gbREV02         1GB      64MB       NA         NA         TE0745-02-93E31-AZ45_3e_1gbREV021GB64MB       NA         NA         TE0745-02-S01645_3e_1gbREV021GB64MB       NA         NA         
    TE0745-02-S01730_1i_1gbREV021GB64MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-71I31-AZ30_1i_1gbREV021GB64MB       NA         NA         smaller FPGA has less MGTs
    TE0745-02-S01830_1i_1gb
    1GB64MBNANAless MGT
    TE0745-
    02
    03-71I31-
    S019
    AK
    45
    30_
    2i
    1i_1gb
    REV02
    REV031GB64MBNANAless MGT
    TE0745-03-
    02
    72I31-
    S020
    A
    45
    30_2i_1gb
    REV02
    REV031GB64MBNANAless MGT
    TE0745-03-
    02
    81C31-
    S021
    A
    45
    35_
    2i
    1c_1gb
    REV02
    REV031GB64MBNANANA
    TE0745-03-
    02
    82I31-
    S022
    A
    45
    35_2i_1gb
    REV02
    REV031GB64MBNANANA
    TE0745-
    02
    03-
    81C31
    91C31-
    AZ
    A
    35
    45_1c_1gb
    REV02
    REV031GB64MBNANANA
    TE0745-
    02
    03-91C31-
    AZ
    AN45_1c_1gb
    REV02
    REV031GB64MBNANANA
    TE0745-
    02
    03-92I31-
    AZ
    A45_2i_1gb
    REV02
    REV031GB64MBNANANA
    TE0745-
    02
    03-92I31-
    S014C1
    AK45_2i_1gb
    REV02
    REV031GB64MBNANA
    without PLL
    NA
    TE0745-03-
    02
    93E31-
    S014C2
    A45_
    2i
    3e_1gb
    REV02
    REV031GB64MBNANA
    without PLL
    NA
    TE0745-
    02
    03-93E31-
    S014C3
    AK45_
    2i
    3e_1gb
    REV02
    REV031GB64MBNA
    without PLL
    NANA

    *used as reference


    Design supports following carriers:

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    titleHardware Carrier

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    Carrier ModelNotes
    TEB0745*

    *used as reference

    Additional HW Requirements:

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    Additional HardwareNotes
    USB Cable for JTAG/UARTCheck Carrier Board and Programmer for correct type
    XMOD ProgrammerCarrier Board dependent, only if carrier has no own FTDI

    *used as reference

    Content

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    Notes :

    • content of the zip file

    For general structure and of the reference design, see see Project Delivery - AMD devices

    Design Sources

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    TypeLocationNotes
    Vivado<project folder>\block_design
    <project folder>\constraints
    <project folder>\ip_lib
    <project folder>\board_files
    Vivado Project will be generated by TE Scripts
    Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation
    PetaLinux<project folder>\os\petalinuxPetaLinux template with current configuration


    Additional Sources

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    TypeLocationNotes
    SI5338<project folder>\misc\PLL\Si5338_BSI5338 Project with current PLL Configuration
    init.sh<project folder>\misc\sd\Additional Initialization Script for Linux


    Prebuilt

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    Notes :

    • prebuilt files
    • Template Table:

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        File

        File-Extension

        Description

        BIF-File*.bifFile with description to generate Bin-File
        BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
        BIT-File*.bitFPGA (PL Part) Configuration File
        Boot Script-File*.scr

        Distro Boot Script file

        DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

        Debian SD-Image

        *.img

        Debian Image for SD-Card

        Diverse Reports---Report files in different formats
        Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
        Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
        LabTools Project-File*.lprVivado Labtools Project File

        MCS-File

        *.mcs

        Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

        MMI-File

        *.mmi

        File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

        OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
        Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

        SREC-File

        *.srec

        Converted Software Application for MicroBlaze Processor Systems





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    File

    File-Extension

    Description

    BIF-File*.bifFile with description to generate Bin-File
    BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
    BIT-File*.bitFPGA (PL Part) Configuration File
    Boot Script-File*.scr

    Distro Boot Script file

    DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
    Diverse Reports---Report files in different formats
    Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
    Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
    LabTools Project-File*.lprVivado Labtools Project File
    OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
    Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


    Download

    Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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    Reference Design is available on:

    Design Flow

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    Notes :
    • Basic Design Steps

    • Add/ Remove project specific description


    Note

    Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

    See also:

    The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

    TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

    Note

    Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

      Code Block
      languagebash
      themeMidnight
      title_create_win_setup.cmd/_create_linux_setup.sh
      ------------------------Set design paths----------------------------
      -- Run Design with: _create_win_setup
      -- Use Design Path: <absolute project path>
      --------------------------------------------------------------------
      -------------------------TE Reference Design---------------------------
      --------------------------------------------------------------------
      -- (0)  Module selection guide, project creation...prebuilt export...
      -- (1)  Create minimum setup of CMD-Files and exit Batch
      -- (2)  Create maximum setup of CMD-Files and exit Batch
      -- (3)  (internal only) Dev
      -- (4)  (internal only) Prod
      -- (c)  Go to CMD-File Generation (Manual setup)
      -- (d)  Go to Documentation (Web Documentation)
      -- (g)  Install Board Files from Xilinx Board Store (beta)
      -- (a)  Start design with unsupported Vivado Version (beta)
      -- (x)  Exit Batch (nothing is done!)
      ----
      Select (ex.:'0' for module selection guide):


    2. Press 0 and enter to start "Module Selection Guide"
    3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
      • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

        Note

        Note: Select correct one, see also Vivado Board Part Flow


    4. Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder

      Code Block
      languagepy
      themeMidnight
      titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
      TE::hw_build_design -export_prebuilt


      Info

      Using Vivado GUI is the same, except file export to prebuilt folder.


    5. Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
      • use TE Template from "<project folder>\os\petalinux"
      • use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.

      • The build images are located in the "<plnx-proj-root>/images/linux" directory

    6. Configure the boot.scr file as needed, see Distro Boot with Boot.scr

    7. Generate Programming Files with Vitis
      1. Copy PetaLinux build image files to prebuilt folder
        • copy u-boot.elf,
       
        • system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
          Info

          "<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>"

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          This step depends on Xilinx Device/Hardware

          for Zynq-7000 series

          • copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

          for ZynqMP

          • copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder

          for Microblaze

          • ...
      1. Generate Programming Files

      with Vitis
      1. Code Block
        languagepy
        themeMidnight
        titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
        TE::sw_run_vitis -all
        TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


        Note

        TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis


    Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart

    Launch

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    Note:

    • Programming and Startup procedure

    Programming

    Note

    Check Module and Carrier TRMs for proper HW configuration before you try any design.

    Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

    Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

    Get prebuilt boot binaries

    1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
    2. Press 0 and enter to start "Module Selection Guide"
      1. Select assembly version
      2. Validate selection
      3. Select create and open delivery binary folder

        Info

        Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


    QSPI-Boot mode

    Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.

    1. Connect JTAG and power on carrier with module
    2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

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      titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
      TE::pr_program_flash -swapp u-boot
      TE::pr_program_flash -swapp hello_te0745 (optional)


    3. Copy image.ub and boot.scr on SD or USB
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    4. Set Boot Mode to QSPI-Boot and insert SD or USB.
      • Depends on Carrier, see carrier TRM.

    SD-Boot mode

    1. Copy image.ub, boot.scr and Boot.bin on SD
      • use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
      • or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
    2. Set Boot Mode to SD-Boot.
      • Depends on Carrier, see carrier TRM.
    3. Insert SD-Card in SD-Slot.

    JTAG

    Not used on this Example.

    Usage

    1. Prepare HW like described on section Programming
    2. Connect UART USB (most cases same as JTAG)
    3. Select SD Card as Boot Mode (or QSPI - depending on step 1)

      Info

      Note: See TRM of the Carrier, which is used.


      Tip

      Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable.
      The boot options described above describe the common boot processes for this hardware; other boot options are possible.
      For more information see Distro Boot with Boot.scr


    4. Power On PCB

      Expand
      titleboot process

      1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

      2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


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      This step depends on Xilinx Device/Hardware

      for Zynq-7000 series

      1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


      for ZynqMP???

      1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM,

      2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR,

      3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR


      for Microblaze with Linux

      1. FPGA Loads Bitfile from Flash,

      2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available)

      3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while),

      4. U-boot loads Linux from QSPI Flash into DDR


      for native FPGA

      ...


    Linux

    1. Open Serial Console (e.g. putty)
      • Speed: 115200
      • select COM Port

        Info

        Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)


    2. Linux Console:

      Code Block
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      # password default disabled with 2021.2 petalinux release
      petalinux login: root
      Password: root


      Info

      Note: Wait until Linux boot finished


    3. You can use Linux shell now.

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      i2cdetect -y -r 0	(check I2C 0 Bus)
      dmesg | grep rtc	(RTC check)
      udhcpc				(ETH0 check)
      lsusb				(USB2.0 check)


    4. Option Features

      • Webserver to get access to Zynq
        • insert IP on web browser to start web interface
      • init.sh scripts
        • add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD"
        • Script will enable SFP interface after linux booting, if file is copied on SD

    Vivado HW Manager

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    Note:

    • Add picture of HW Manager

    • add notes for the signal either groups or topics, for example:

      Control:

      • add controllable IOs with short notes..

      Monitoring:

      • add short notes for signals which will be monitored only
      • SI5338 CLKs:
        • Set radix from VIO signals to unsigned integer.
          Note: Frequency Counter is inaccurate and displayed unit is Hz
        • expected CLK Frequency...
    Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
    • Monitoring:

      • SI5338 CLKs: 

        • Set radix from VIO signals to unsigned integer.
          Note: Frequency Counter is inaccurate and displayed unit is Hz
          , SI5338 CLK (0 and 3) are configured to 125MHz by default.


    Scroll Title
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    titleVivado Hardware Manager

    System Design - Vivado

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    Note:

    • Description of Block Design, Constrains... BD Pictures from Export...

    Block Design

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    titleBlock Design


    *clk3 is not available on the smallest SOC (xc7z030)


    PS Interfaces

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    Note:

    • optional for Zynq / ZynqMP only

    • add basic PS configuration

    Activated interfaces:

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    titlePS Interfaces

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    TypeNote
    DDR
    QSPIMIO
    ETH0MIO
    USB0MIO
    SD0MIO
    UART0MIO
    I2C0MIO
    GPIOMIO
    ETH0 ResetMIO
    USB0 ResetMIO
    I2C0 ResetMIO
    TTC0..1EMIO
    SWDT0EMIO


    Constrains

    Basic module constrains

    Code Block
    languageruby
    title_i_bitgen_common
    set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
    set_property CONFIG_VOLTAGE 1.8 [current_design]
    set_property CFGBVS GND [current_design]

    Design specific constrain

    Code Block
    languageruby
    title_i_timing.xdc
    set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk0_clk_p]
    set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk3_clk_p]
    set_false_path -from [get_clocks si5338_clk0_clk_p] -to [get_clocks clk_fpga_0]
    set_false_path -from [get_clocks si5338_clk3_clk_p] -to [get_clocks clk_fpga_0]

    Software Design - Vitis

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    Note:
    • optional chapter separate

    • sections for different apps

    For Vitis project creation, follow instructions from:

    Vitis

    Application

    follow instructions from:

    Vitis

    Application

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    ----------------------------------------------------------

    FPGA Example

    ----------------------------------------------------------FPGA Example

    scu

    MCS Firmware to configure SI5338 and Reset System.

    srec_spi_bootloader

    TE modified 20192023.2 SREC

    Bootloader to load app or second bootloader from flash into DDR

    Descriptions:

    • Modified Files: blconfig.h, bootloader.c
    • Changes:
      • Add some console outputs and changed bootloader read address.
      • Add bugfix for 2018.2 qspi flash

    xilisf_v5_11

    TE modified 20192023.2 xilisf_v5_11

    Changed default Flash type to 5.

    _11

    • Changed default Flash type to 5.


    ----------------------------------------------------------

    Zynq Example:

    ----------------------------------------------------------Zynq Example:

    zynq_

    fsbl

    TE modified 20192023.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_fsbl_hooks.h/.c (for hooks and board)\n\

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  uboot platform-top.h)
      • CPLD access
      • Read CPLD Firmware and SoC Type
      • Configure Marvell PHY

    zynq_fsbl_flash

    TE modified 2019.2 FSBL

    General:

  • Modified Files: main.c
  • General Changes:
  •  Display FSBL Banner
  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation


    ----------------------------------------------------------

    ZynqMP Example:

    ----------------------------------------------------------

    zynqmp_fsbl

    TE modified 20192023.2 FSBL

    General:

    • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
    • Add Files:   te_xfsbl_hooks.h/.c (for hooks and board)\n\
    • General Changes: 
      • Display FSBL Banner and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIO

    zynqmp_fsbl_flash

    TE modified 2019.2 FSBL

    General:

    • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c.c (for hooks and board)
    • General Changes: 
      •  Display Display FSBL Banner
      • Set FSBL Boot Mode to JTAG
      • and Device Name

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+OTG Reset over MIODisable Memory initialisation


    zynqmp_pmufw

    Xilinx default PMU firmware.firmware.

    ----------------------------------------------------------

    General Example:

    ----------------------------------------------------------General Example:

    hello_te0820

    Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis  Vitis is used to generate Boot.bin.

    Template location: "<project folder>\sw_lib\sw_apps\"

    fsbl

    TE modified 20212023.2 FSBL

    General:

    • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
    • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

    • General Changes: 
      • Display FSBL Banner and Device ID

    Module Specific:

    • Add Files: all TE Files start with te_*
      • Si5338 Configuration
      • ETH+USB Reset over MIO

    hello_te0745

    Hello TE0745 is a Xilinx Hello World example as endless loop instead of one console output.

    u-boot

    U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

    Software Design -  PetaLinux

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    Note:
    • optional chapter separate

    • sections for linux

    • Add "No changes." or "Activate: and add List"

    For PetaLinux installation and project creation, follow instructions from:

    Config

    Start with petalinux-config or petalinux-config --get-hw-description

    Changes:

    • MAC from eeprom together with uboot and device tree settings:
      • CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC=""
    • add new flash partition for bootscr and sizing
      • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
      • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2PART1_SIZE=0x1400000
      • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME="bootscr"
      • CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_SIZE=0x40000
    • Identification
      • CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
      • CONFIG_SUBSYSTEM_PRODUCT="TE0745_TEB0745"

    U-Boot

    Start with petalinux-config -c u-boot

    Changes:

    • MAC from eeprom together with uboot and device tree settings:
      • CONFIG_ENV_OVERWRITE=y
      • CONFIG_NVMEM=y
      • CONFIG_DM_RTC=y    (needed for nvmem driver because of bug in uboot)
    • Boot Modes:
      • CONFIG_QSPI_BOOT=y
      • CONFIG_SD_BOOT=y
      • CONFIG_ENV_IS_IN_FAT is not set
      • # CONFIG_ENV_IS_IN_NAND is not set
      • CONFIG_ENV_IS_IN_SPI_FLASH is not set
      • CONFIG_BOOT_SCRIPT_OFFSET=0x1E20000_SCRIPT_OFFSET=0x1E20000
    • Identification
      • CONFIG_IDENT_STRING=" TE0745_TEB0745"


    Change platform-top.h:

    Code Block
    languagejs
    #include <configs/zynq-common.h>
    #no changes

    Device Tree

    Code Block
    languagejs
    titleproject-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi
    /include/ "system-conf.dtsi"
    
    
    /*--------------------------- QSPI -----------------------*/
    &qspi {
        		#address-cells = <1>;
        		#size-cells = <0>;
        		status = "okay";
        		flash0: flash@0 {
            				compatible = "jedec,spi-nor";
            				reg = <0x0>;
    				#address-cells = <1>;
    				#size-cells      #address-cells= <1>;
    				
    				spi-rx-bus-width = <1><4>;
    				spi-tx-bus-width        #size-cells= <4>;
    				spi-max-frequency = <1><90000000>;
        		};
    };
    
    
    /*-------------------------- ETH PHY ---------------------*/
    &gem0 {
    	phy-handle = <&phy0>;
      
      nvmem-cells = <&eth0_addr>;
      nvmem-cell-names = "mac-address";  
       = <&phy0>;
    	
    	nvmem-cells = <&eth0_addr>;
    	nvmem-cell-names = "mac-address";
    
    	//required otherwise petalinux gives a static MAC address, this can also be achieved by setting petalinux CONFIG_SUBSYSTEM_ETHERNET_[XXXX]_MAC to an empty string
    	/delete-property/ local-mac-address;  
    	
    	mdio {
    		#address-cells = <1>;
    		#size-cells = <0>;
    		phy0: phy@1 {
    			compatible = "marvell,88e1510";
    			device_type = "ethernet-phy";
    			reg = <1>;
    		} ;
    	} ;
    };
    
    /*---------------------------- USB ----------------------*/
    /{
    	usb_phy0: usb_phy@0 {
    		compatible = "ulpi-phy";
    		#phy-cells = <0>;
    		reg = <0xe0002000 0x1000>;
    		view-port = <0x0170>;
    		drv-vbus;
    	};
    };
    
    &usb0 {
        		dr_mode = "host";
        		//dr_mode = "peripheral";
        		usb-phy = <&usb_phy0>;
    };
    
    
    /*---------------------------- I2C -----------------------*/
    &i2c0 {
    	
      	rtc@6F {
    		compatible = "isil,isl12022";
    		reg = <0x6F>;
    	};
    	  
      	//MAC EEPROM
    	eeprom: eeprom@53 {
    		  compatible = "microchip,24aa025", "atmel,24c02";
    		  reg = <0x53>;
        
        		
    		#address-cells = <1>;
        		#size-cells = <1>;
        		eth0_addr: eth-mac-addr@FA {
        		  reg = <0xFA 0x06>;
        		};    
        
    		
    	};
        
    	i2cmux_SFP: i2cmux@72  {
    		compatible = "nxp,pca9548";
    		reg = <0x72>;
    
    		SFP@0 {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <0>;
    		};
    		SFP@1 {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <1>;
    		};
    		SFP@2 {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <2>;
    		};
    		SFP@3 {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <3>;
    		};
    		SFP@4 {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <4>;
    		};
    		SFP@5 {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <5>;
    		};
    		SFP@6 {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <6>;
    		};
    		SFP@7 {
    			#address-cells = <1>;
    			#size-cells = <0>;
    			reg = <7>;
    		};
    	};
    
    };
         

    Kernel

    Start with petalinux-config -c kernel

    Changes:

    • for Real Time Clock ISL12020MIRZ
      • CONFIG_RTC_DRV_ISL12022=y

    Rootfs

    Start with petalinux-config -c rootfs

    Changes:

    • For web server app:
      • CONFIG_busybox-httpd=y
    • For additional test tools only:
      • CONFIG_i2c-tools=y
      • CONFIG_packagegroup-petalinux-utils=y    (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
    • For auto login:
      • CONFIG_imagefeature-serial-autologin-root=y

    FSBL patch (alternative for vitis fsbl trenz patch)

    See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"

    Petalinux Troubleshoot#Petalinux2023.2

    Applications

    See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"

    startup

    Script App to load init.sh from SD Card if available.

    webfwu

    Webserver application suitable for Zynq access. Need busybox-httpd

    Additional Software

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    Note:
    • Add description for other Software, for example SI CLK Builder ...
    • SI5338 and SI5345 also Link to:

    SI5338

    File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"

    General documentation how you work with this project will be available on Si5338

    Appx. A: Change History and Legal Notices

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    Document Change History

    To get content of older revision go to "Change History" of this page and select older document revision number.

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    • Note this list must be only updated, if the document is online on public doc!
    • It's semi automatically, so do following
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      • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

      • Metadata is only used of compatibility of older exports


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    DateDocument Revision

    Authors

    Description

    Page info
    modified-date
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    dateFormatyyyy-MM-dd

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    infoTypeCurrent version
    dateFormatyyyy-MM-dd
    prefixv.
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    dateFormatyyyy-MM-dd
    typeFlat

    • Release 2023.2
    • new assembly variants
    2023-04-25v.15Manuela Strücker
    • new assembly variants
    2023-02-08v.14Manuela Strücker
    • Release 2021.2
    • new assembly variants
    • added jtag2axi for test purposes
    2020-03-30v.13John Hartfiel
    • Release 2019.2
    2019-09-18v.12John Hartfiel
    • bugfix for TE0745-02-45-3EA
    2018-12-19v.11John Hartfiel
    • documentation notes

    2018-11-26

    v.10John Hartfiel
    • update 2018.2
    • documentation style update

    2018-04-09

    v.7John Hartfiel
    • Typo correction
    2018-02-09v.6John Hartfiel
    • Release 2017.2
    2017-09-11v.1John Hartfiel
    • Initial release
    --all

    Page info
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    dateFormatyyyy-MM-dd
    typeFlat

    --


    Legal Notices

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    IN:Legal Notices



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