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Figure 15: Block diagram of the EDDP.


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FPGA resources utilization

An excerpt of the FPGA resource utilization by the FOC SDSoC Application Project is shown in the Table 2. The FPGA used on the Controller Board is Xilinx 7z010clg400-1.

The power draw of the design is about 250mW as measured by the increase of the power draw of the Control Board when the FPGA is configured with the design.

TypeUsedAvailableUtil%
Slice LUTs57581760032.72
Slice Registers72773520020.67
F7 Muxes3388000.38
RAMB36/FIFO216035
RAMB1841203.33
DSP48E1348042.50
BUFGCTRL43212.50
MMCME2_ADV1250

Table 2: FPGA resources utilization.


List of additional documents

The additional documents, listed in the Table 23,  can be downloaded from Trenz EDDP Web Hub:

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TitleDescription
FOC SDSoCImplementation of a Field-Oriented Control algorithm in C++ with Vivado SDSoC
SDSoC Hardware Platform ARTY-Z7A basis for building Vivado SDSoC applications running on an Arty-Z7 board connected to a TEC0053 board
AXI4-Stream AD7403An IP core for filtering the delta-sigma bitstream read from one or more ADC-s of type of AD7403 to an AXI4-Stream of samples
AXI4-Stream EncoderAn IP core for converting impulses from a relative index encoder with an index signal to an AXI4-Stream of position and speed data
AXI4-Stream PWMAn IP core for generating PWM signals according to the input AXI4-Stream
AXI4-Stream ConcatAn IP core for concatenating AXI4-Streams
Web GUIA Web UI to control and monitor an EDPS Board over the Network API
Network APIA communication protocol, based on Websockets, to control an EDPS board
Embedded Linux CodeA server program interfacing to an EDPS board and implementing the Network API and the functions of a Web Server

Table 23: List of additional documents.

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd



Jan KumannGeneral formatting changes and small corrections.

2017-08-14

v.10

Antti Lukats, Andrei Errapart

Initial document.

Table 24: Document change history.

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