Page History
...
| Pin Schematic Name | XMOD Header JX1 Pin | B2B | Note |
|---|---|---|---|
| TCK | C (pin 4) | JM1-90 | - |
| TDO | D (pin 8) | JM1-88 | - |
| TDI | F (pin 10) | JM1-86 | - |
| TMS | H (pin 12) | JM1-92 | - |
| B14_L25 | A (pin 3) | JM2-97 | UART -RX (receive line(output from module to XMOD Programmer) |
| B14_L0 | B (pin 7) | JM2-99 | UART -TX (transmit line(input to module from XMOD Programmer) |
| BOOTMODE | E (pin 9) | JM2-100 | - |
| PROG_B | G (pin 11) | JM1-94 | - |
...
V_CFG Value | Jumper J27 Setting | Note |
|---|---|---|
| 1.8V | pins 1-2 connected | Module's output voltage. |
| V_CFG0* | pins 3-4 connected | Internal module VCCIO: 3.3V or 1.8V (Settable by 0-Ohm-Resistor on TE0714 module). |
| 3.3V_OUT | pins 5-6 connected | Module's output voltage. |
*Default setting, do not changed, if V_CFG0 Bank power is sourced by module itself.
Table 8: Setting of reference I/O-voltage XMOD header.
| Note |
|---|
Use Xilinx compatible TE0790 adapter board (designation TE-0790-xx with out 'L') to program the Xilinx Zynq devices. The TE0790 adapter board's CPLD have to be configured with the Standard variant of the firmware. Refer to the TE0790 Resources Site for further information and firmware download. |
...
| Pin Schematic Name | Header J3 Pin | B2B | Note |
|---|---|---|---|
| TCK | 4 | JM1-90 | - |
| TDO | 8 | JM1-88 | - |
| TDI | 10 | JM1-86 | - |
| TMS | 12 | JM1-92 | - |
| B14_L25 | 3 | JM2-97 | UART -RX (receive line(output from module) |
| B14_L0 | 7 | JM2-99 | UART -TX (transmit line(input to module) |
| BOOTMODE | 9 | JM2-100 | - |
| PROG_B | 11 | JM1-94 | - |
| XADC_P | 13 | JM1-25 | Analog input differential pair |
| XADC_N | 14 | JM1-27 | |
| CLK0_N | 15 | JM1-4 | AC decoupled on-board (100 nF capacitor) |
| CLK0_P | 16 | JM1-2 |
...
| UART Signal Schematic Name | B2B | XMOD Header JX1 | Pin Header J3 | Note |
|---|---|---|---|---|
| B14_L0 | JM2-99 | JX1-7 | J3-7 | UART -TX (transmit line(input to module) |
| B14_L25 | JM2-97 | JX1-3 | J3-3 | UART -RX (receive line(output from module) |
Table 10: UART interface signals.
...
| Module Connector (B2B) Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| JM1 | 3.3V | Out | 97, 99 | 3.3V module supply voltage |
| 3.3V_OUT | In | 83 | 3.3V module output voltage | |
| VCCIO34 | Out | 61 | PL IO-bank VCCIO | |
| JM2 | 1.8V | In | 18 | 1.8V module output voltage |
| 3.3V_OUT | Out | 54 | 3.3V module output voltage | |
| V_CFG0 | In/out | 53 | Direction depends on solder option of the modul: Internal module VCCIO : 3.3V or 1.8V or source from carrier is possible |
Table 16: Power pin description of B2B module connector.
...
| On-board Pin Header Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J17 | 3.3V | In / Out | 5, 46 | 3.3V external supply voltage |
| V_CFG | Out / int | 6, 45 | VCCIO, direction depends on jumper 27 settings and module solder option | |
| J20 | 3.3V | In / Out | 5, 46 | 3.3V external supply voltage |
| VCCIO34 | In / Out | 6, 45 | PL IO-bank VCCIO, depends on Jumper settings |
...
| Jumper / Header Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| J26 | VCCIO34 | In | 1, 3, 5 | - |
| 1.8V | Out | 2 | - | |
| 2.5V | Out | 4 | - | |
| 3.3V_OUT | Out | 6 | - | |
| J27 | V_CFG | In / Out | 1, 3, 5- | direction depends on jumper 27 settings and module solder option |
| 1.8V | Out | 2 | - | |
| V_CFG0 | Out | 4 | - | |
| 3.3V_OUT | Out | 6 | - |
...
| JTAG/UART Header Designator | VCC / VCCIO | Direction | Pins | Notes |
|---|---|---|---|---|
| JX1 (XMOD) | 3.3V | Out | 5 | Connected to 3.3V external supply voltage |
| VIO | Out | 6 | Connected to 'V_CFG', depends on jumper 27 settings | |
| J3 | 3.3V | Out | 5 | Connected to 3.3V external supply voltage |
| V_CFG | Out | 6 | VCCIO, direction depends on jumper 27 settings and module solder option |
Table 19: Power pin description of XMOD/JTAG Connector.
...
Overview
Content Tools