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General Design description
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Zynq PS Design with Linux Example. Add simple frequency counter to measure SI5338 Reference CLK and RGPIO IP to get access to CPLD IOs with Vivado HW-Manager.

Key Features

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Excerpt
  • PetaLinux
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter
  • RGPIO (Beta)
  • PL MIG
  • Modified FSBL for SI5338 programming
  • Special FSBL for QSPI programming

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DateVivadoProject BuiltAuthorsDescription
2018-06-012017.4
John Hartfielinitial release

Release Notes and Know Issues

TE0783-test_board_noprebuilt-vivado_2017.4-build_10_20180611114036.zip
TE0783-test_board-vivado_2017.4-build_10_20180611114017.zip		John Hartfielinitial release

Release Notes and Know Issues

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  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root

Vivado HW Manager

SI5338 MGT Reference CLKs: 

  1. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. RTC check: dmesg | grep rtc
    3. ETH0 works with udhcpc
    4. USB type  "lsusb" or connect USB2.0 device

Vivado HW Manager

SI5338 MGT Reference CLKs: 

  • Open Vivado HW-Manager Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).
  • Set radix from VIO signals to unsigned integer.
    Note: Frequency Counter is inaccurate and displayed unit is Hz
  • SI5338 CLK is CLKs are configured to  to 125MHz with example FSBL initialisation.

PL MIG Status Signals

TODO Bild

System Design - Vivado

Status signal:

  • Status signals connected to VIO

Image Added

Custom LED

Red LED D1 can be controlled via VIO.

Image Added

RGPIO

RGPIO Pins can be controlled via VIO

Image Added

System Design - Vivado

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PS Interfaces

TypNote
DDR3
QSPIMIO
ETH0MIO
USB0MIO
SD0MIO
SD1MIO
I2C0MIO
SWDT0..1
TTC0..3


Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Design specific constrain

_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

Design specific constrain

Code Block
languageruby
title_i_io.xdc
#set_property PACKAGE_PIN AA8 [get_ports {SI_MGT_CLK0_110_clk_p[0]}]
#set_property PACKAGE_PIN N8 [get_ports {SI_MGT_CLK0_112_clk_p[0]}]
#set_property PACKAGE_PIN AF10 [get_ports {SI_MGT_CLK1_109_clk_p[0]}]
#set_property PACKAGE_PIN W8 [get_ports {SI_MGT_CLK1_111_clk_p[0]}]
#set_property IOSTANDARD DIFF_SSTL15 [get_ports {MIG_SYS_CLK_clk_p[0]}]
#set_property PACKAGE_PIN H9 [get_ports {MIG_SYS_CLK_clk_p[0]}]
# -------------
#LED
set_property PACKAGE_PIN AE20 [get_ports {LED[0]}]
set_property IOSTANDARD LVCMOS33 [get_ports {LED[0]}]
# -------------
#RGPIO
set_property PACKAGE_PIN AB19 [get_ports RGPIO_M_EXT_0_clk]
set_property PACKAGE_PIN AB20 [get_ports RGPIO_M_EXT_0_rx]
set_property PACKAGE_PIN AD20 [get_ports RGPIO_M_EXT_0_tx]
set_property IOSTANDARD LVCMOS33 [get_ports RGPIO_M_EXT_0_clk]
set_property IOSTANDARD LVCMOS33 [get_ports RGPIO_M_EXT_0_rx]
set_property IOSTANDARD LVCMOS33 [get_ports RGPIO_M_EXT_0_tx]
_i_io.xdc
Code Block
languageruby
title_i_fm.xdc
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_1/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_2/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks {zsys_i/util_ds_buf_3/U0/IBUF_OUT[0]}]
set_false_path -from [get_clocks {zsys_i/util_ds_buf_0/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks {zsys_i/util_ds_buf_1/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks {zsys_i/util_ds_buf_2/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks {zsys_i/util_ds_buf_3/U0/IBUF_OUT[0]}] -to [get_clocks clk_fpga_0]
Code Block
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title
Software Design - SDK/HSI
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Work in progress
  • Release 2017.4
2018-05-30v.1
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  • Initial release

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