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Template Revision 2.6 8 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vivado 20182019.32
  • UART
  • I2C
  • FMeter
  • Modified FSBL for DDR Less Zynq
  • Modified FSBL for DDR Less Zynq + small app with LED+Sensor access
  • Special FSBL for QSPI programming

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titleDesign Revision History

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DateVivadoProject BuiltAuthorsDescription
2020-04-162019.2TE0722-test_board_noprebuilt-vivado_2019.2-build_10_20200416064916.zip
TE0722-test_board-vivado_2019.2-build_10_20200416064756.zip
John Hartfiel
  • 2019.2 update
2019-05-222018.3TE0722-test_board-vivado_2018.3-build_05_20190522113216.zip
TE0722-test_board_noprebuilt-vivado_2018.3-build_05_20190522113228.zip
John Hartfiel
  • split FSBL into 2 templates, one with and one without  Sensor+LED access example app
2019-05-142018.3TE0722-test_board-vivado_2018.3-build_05_20190510163659.zip
TE0722-test_board_noprebuilt-vivado_2018.3-build_05_20190510163900.zip
John Hartfiel
  • TE Script update
  • rework of the FSBLs
    • DDR LESS, Device ID, Sensor+LED access
  • VIO for RGB access
2018-08-142018.2TE0722-test_board-vivado_2018.2-build_02_20180815123557.zip
TE0722-test_board_noprebuilt-vivado_2018.2-build_02_20180815123610.zip
John Hartfiel
  • initial release


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IssuesDescriptionWorkaroundTo be fixed versionNo known issues------
---Flash Programming failed with 19.2Depending on Flash content Flash programming failed with provided fsbl_flash (Xilinx AR# 70548 ) 2019.2 version
  • Option1:
    • In case Flash is empty, use fsbl_flash on programming GUI 
    • In case Flash is programmed use normal fsbl on programming GUI
  • Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3


Requirements

Software

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Notes :

  • list of software which was used to generate the design

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titleSoftware

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SoftwareVersionNote
VivadoVitis20182019.32needed
SDK2018.3needed
, Vivado is included into Vitis installation


Hardware

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Notes :

  • list of software which was used to generate the design

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0722-01        10REV01        0GB       16MB       NA        NA     NA     
TE0722-02        10REV02        0GB       16MB       NA        NA     NA     
TE0722-02I       10_i       REV02        0GB       16MB       NA        NA     NA     
TE0722-02IC7   10_i_c7REV02        0GB       16MB       NA        "without SD"NA     
TE0722-02-07S-1C 7s         REV02        0GB       16MB       NA        NA     NA     


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titleDesign sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSIVitis<design name>/sw_libAdditional Software Template for SDK/HSI Vitis and apps_list.csv with settings automatically for HSIVitis app generation


Additional Sources

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TypeLocationNotes
------


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Notes :

  • prebuilt files
  • Template Table:

    • Scroll Title
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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfxsaExported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems



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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfxsaExported Vivado Hardware Specification for SDK/HSI Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


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Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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  • Important set new Vivado version link on every Design update of new vivado version!
  • Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/
en/TE080320171/Starterkit   -->

Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description

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  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter to start "Module Selection Guide"
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
    1. (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF XSA and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Generate Programming Files with HSI/SDKVitis
    1. Run on Vivado TCL: TE::sw_run_hsivitis -all
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_

      sdk

      vitis
      Note:  TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis 
      Projects contains 3 FSBL template: zynq_fsbl (FSBL modified for DDR Less application → use for Boot.bin), zynq_fsbl_app (FSBL modified for DDR Less application and with demo app included → create Boot with this FSBL and Bitstream only), zynq_fsbl_flash(FSBL modified for Flash programming →FSBL which must be selected separately to program Flash)

      See SDK Projects

      Info

      TE0722  is without DDR, so special FSBL (sources on reference designs) is needed, see also: DDR less ZYNQ Design


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Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debuggingand debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select Create and open delivery binary folder
      Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated

QSPI

Optional for Boot.bin on QSPI Flash and image.ub on SD.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash _binfile -swapp zynq_fsbl_appu-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
              optional "TE::pr_program_flash -swapp zynq_fsbl_flash) on setupapp" possible

SD

Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot only. See also Xilinx AR#66846

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  1. Prepare HW like described on section 68616275
  2. Connect UART USB (most cases same as JTAG)
  3. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from QSPI into OCM, 2. FSBL loads bitfile from qsiQSPI, 3. FSBL starts application (included into the FSBL Code)

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Code Block
languageruby
title_i_io.xdc
#RGB LED
#R
set_property PACKAGE_PIN J15 [get_ports {RGB_LED[0]}]
#G
set_property PACKAGE_PIN L14 [get_ports {RGB_LED[1]}]
#B
set_property PACKAGE_PIN K12 [get_ports {RGB_LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGB_LED[*]}]

Software Design -

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Vitis

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Note:
  • optional chapter separate

  • sections for different apps

For SDK project creation, follow instructions from:SDK Projects

Vitis

Application

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FPGA Example

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 20182019.3 2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 20182019.3 2 xilisf_v5_11

  • Changed default Flash type to 5.

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Zynq Example:

zynq_fsbl

TE modified 20182019.3 2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot  platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY

zynq_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
  • Add Files:  te_xfsbl_hooks.h/.c (for hooks and board)\n\
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation


zynqmp_pmufw

Xilinx default PMU firmware.

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General Example:

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI Vitis  is used to generate Boot.bin.

Source location: \sw_lib\sw_apps

zynq_fsbl

TE modified 20182019.3 2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID
    • Disable Memory initialisation on main.c

zynq_fsbl_app

TE modified 20182019.3 2 FSBL

General:

  • Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\

  • General Changes: 
    • Display FSBL Banner and Device ID
    • Disable Memory initialisation on main.c

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zynq_fsbl_flash

TE modified 20182019.3 2 FSBL

General:

  • Modified Files: main.c
  • General Changes:
    •  Display FSBL Banner
    • Set FSBL Boot Mode to JTAG
    • Disable Memory initialisation

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DateDocument Revision

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Description

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  • 2019.2 release
2020-04-16v.7John Hartfiel
  • separate template for FSBL with App included
2019-05-14v.6John Hartfiel
  • 2018.3 release
2018-08-15v.5John Hartfiel
  • 2018.2 release
--all

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