Page History

Template Revision 2.0 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"

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Important General Note:

• Export PDF to download, if vivado revision is changed!

• Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

  • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

    • Figure template:

      Scroll Title
      anchor Figure_x title Figure x: Text
      Scroll Ignore Create DrawIO object here: Attention if you copy from other page, use Scroll Only image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

    • Table template:

      • Layout macro can be use for landscape of large tables
      • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

    • Scroll Title
      anchor Table_x title Table x: Text
      Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true Example Comment 1 2

• ...

Table of contents

Notes :

• short description of the PCB

• Short Link of the wiki resources reference:

  • Use short link the Wiki Resource page, for example: http://trenz.org/te0720-info

  • List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Notes :

• Add basic key futures, which can be tested with the design

• PetaLinux
• SD
• ETH
• USB FIFO
• Aurora
• FMeter
• Modified FSBL for SI5345 programming
• Special FSBL for QSPI programming

Notes :

• add every update file on the download
• add design changes on description

• add known Design issues and general notes for the current revision
• do not delete known issue, add fixed version time stamp if  issue fixed

Notes :

• list of software which was used to generate the design

Notes :

• list of software which was used to generate the design

Notes :

• content of the zip file

Notes :

• prebuilt files
• Template Table:

  • Scroll Title
    anchor Table_9 title Table 9: Prebuilt files
    Scroll Table Layout orientation portrait sortDirection ASC repeatTableHeaders default style widths sortByColumn 1 sortEnabled false cellHighlighting true File File-Extension Description BIF-File *.bif File with description to generate Bin-File BIN-File *.bin Flash Configuration File with Boot-Image (Zynq-FPGAs) BIT-File *.bit FPGA (PL Part) Configuration File DebugProbes-File *.ltx Definition File for Vivado/Vivado Labtools Debugging Interface Debian SD-Image *.img Debian Image for SD-Card Diverse Reports --- Report files in different formats Hardware-Platform-Specification-Files *.hdf Exported Vivado Hardware Specification for SDK/HSI and PetaLinux LabTools Project-File *.lpr Vivado Labtools Project File MCS-File *.mcs Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) MMI-File *.mmi File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) OS-Image *.ub Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) Software-Application-File *.elf Software Application for Zynq or MicroBlaze Processor Systems SREC-File *.srec Converted Software Application for MicroBlaze Processor Systems

• Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/TE0712/Reference_Design/2018.2/test_board

• Basic Design Steps

• Add/ Remove project specific description

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Note:

• Programming and Startup procedure

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Note:

• Add picture of HW Manager

• add notes for the signal either groups or topics, for example:
  

  Control:

  • add controllable IOs with short notes..

  Monitoring:

  • add short notes for signals which will be monitored only

  SI5338_CLK0 Counter: 

  Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.Note: Frequency Counter is inaccurate and displayed unit is Hz

Note:

• Description of Block Design, Constrains... BD Pictures from Export...

Note:

• optional for Zynq / ZynqMP only

• add basic PS configuration

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

create_clock -period 12.800 -name GT_CLK1 [get_nets zusys_i/GT_system/aurora_m_left_0/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out]
create_clock -period 12.800 -name GT_CLK2 [get_nets zusys_i/GT_system/aurora_m_right_0/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out]
create_clock -period 12.800 -name GT_CLK3 [get_nets zusys_i/GT_system/aurora_s_left_1/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out]
create_clock -period 12.800 -name GT_CLK4 [get_nets zusys_i/GT_system/aurora_s_left_2/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out]
create_clock -period 12.800 -name GT_CLK5 [get_nets zusys_i/GT_system/aurora_s_right_1/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out]
create_clock -period 12.800 -name GT_CLK6 [get_nets zusys_i/GT_system/aurora_s_right_2/inst/clock_module_i/ultrascale_tx_userclk_1/user_clk_out]


# Test
set_property PACKAGE_PIN W7 [get_ports {TEST_CLK_clk_p[0]}]
set_property PACKAGE_PIN W6 [get_ports {TEST_CLK_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports TEST_CLK_clk_*]

# Bank 44 HD 3.3V

set_property PACKAGE_PIN AF15 [get_ports {LED_FP[0]}]
set_property PACKAGE_PIN AG15 [get_ports {LED_FP[1]}]
set_property PACKAGE_PIN AE15 [get_ports {LED_FP[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports LED_FP*]

# Bank 50 HD 3.3V
#set_property PACKAGE_PIN H11 [get_ports {DAC1_CLK}]
#set_property PACKAGE_PIN F10 [get_ports {DAC1_MODE[0]}]
#set_property PACKAGE_PIN D11 [get_ports {DAC1_D[0]}]
#set_property PACKAGE_PIN D10 [get_ports {DAC1_D[1]}]
#set_property PACKAGE_PIN G11 [get_ports {DAC1_D[2]}]
#set_property PACKAGE_PIN J11 [get_ports {DAC1_D[3]}]
#set_property PACKAGE_PIN G10 [get_ports {DAC1_D[4]}]
#set_property PACKAGE_PIN H10 [get_ports {DAC1_D[5]}]
#set_property PACKAGE_PIN J10 [get_ports {DAC1_D[6]}]
#set_property PACKAGE_PIN E10 [get_ports {DAC1_D[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports DAC1_*]

#set_property PACKAGE_PIN F12 [get_ports {DAC2_CLK}]
#set_property PACKAGE_PIN F11 [get_ports {DAC2_MODE[0]}]
#set_property PACKAGE_PIN G15 [get_ports {DAC2_D[0]}]
#set_property PACKAGE_PIN H14 [get_ports {DAC2_D[1]}]
#set_property PACKAGE_PIN J14 [get_ports {DAC2_D[2]}]
#set_property PACKAGE_PIN G14 [get_ports {DAC2_D[3]}]
#set_property PACKAGE_PIN G13 [get_ports {DAC2_D[4]}]
#set_property PACKAGE_PIN H13 [get_ports {DAC2_D[5]}]
#set_property PACKAGE_PIN H12 [get_ports {DAC2_D[6]}]
#set_property PACKAGE_PIN J12 [get_ports {DAC2_D[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports DAC2_*]

# Bank 44 HD 3.3V
#set_property PACKAGE_PIN AK15 [get_ports {DAC3_CLK}]
#set_property PACKAGE_PIN AK14 [get_ports {DAC3_MODE[0]}]
#set_property PACKAGE_PIN AG14 [get_ports {DAC3_D[0]}]
#set_property PACKAGE_PIN AE13 [get_ports {DAC3_D[1]}]
#set_property PACKAGE_PIN AG13 [get_ports {DAC3_D[2]}]
#set_property PACKAGE_PIN AJ15 [get_ports {DAC3_D[3]}]
#set_property PACKAGE_PIN AJ14 [get_ports {DAC3_D[4]}]
#set_property PACKAGE_PIN AH14 [get_ports {DAC3_D[5]}]
#set_property PACKAGE_PIN AF13 [get_ports {DAC3_D[6]}]
#set_property PACKAGE_PIN AH13 [get_ports {DAC3_D[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports DAC3_*]

#set_property PACKAGE_PIN AL12 [get_ports {DAC4_CLK}]
#set_property PACKAGE_PIN AK13 [get_ports {DAC4_MODE[0]}]
#set_property PACKAGE_PIN AP14 [get_ports {DAC4_D[0]}]
#set_property PACKAGE_PIN AN14 [get_ports {DAC4_D[1]}]
#set_property PACKAGE_PIN AM14 [get_ports {DAC4_D[2]}]
#set_property PACKAGE_PIN AN13 [get_ports {DAC4_D[3]}]
#set_property PACKAGE_PIN AP12 [get_ports {DAC4_D[4]}]
#set_property PACKAGE_PIN AN12 [get_ports {DAC4_D[5]}]
#set_property PACKAGE_PIN AL13 [get_ports {DAC4_D[6]}]
#set_property PACKAGE_PIN AM13 [get_ports {DAC4_D[7]}]
#set_property IOSTANDARD LVCMOS33 [get_ports DAC4_*]

# Bank 64 HP 1.8V
set_property PACKAGE_PIN AL6 [get_ports FIFO_CLK]
set_property IOSTANDARD LVCMOS18 [get_ports FIFO_CLK]
set_property PACKAGE_PIN AM8 [get_ports {FTDI_RESET_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {FTDI_RESET_N}]
set_property PACKAGE_PIN AN8 [get_ports {WAKEUP_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {WAKEUP_N}]

set_property PACKAGE_PIN AJ12 [get_ports {RXF_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {RXF_N}]
set_property PACKAGE_PIN AK12 [get_ports {TXE_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {TXE_N}]
set_property PACKAGE_PIN AM10 [get_ports {BE[0]}]
set_property PACKAGE_PIN AK10 [get_ports {BE[1]}]
set_property PACKAGE_PIN AM11 [get_ports {BE[2]}]
set_property PACKAGE_PIN AL11 [get_ports {BE[3]}]
set_property IOSTANDARD LVCMOS18 [get_ports {BE[*]}]
set_property PACKAGE_PIN AL10 [get_ports {SIWU_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {SIWU_N}]
set_property PACKAGE_PIN AM9 [get_ports {WR_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {WR_N}]
set_property PACKAGE_PIN AK9 [get_ports {RD_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {RD_N}]
set_property PACKAGE_PIN AL8 [get_ports {OE_N}]
set_property IOSTANDARD LVCMOS18 [get_ports {OE_N}]

set_property PACKAGE_PIN AK1  [get_ports {DATA[0]}]
set_property PACKAGE_PIN AJ10 [get_ports {DATA[1]}]
set_property PACKAGE_PIN AJ9  [get_ports {DATA[2]}]
set_property PACKAGE_PIN AK7  [get_ports {DATA[3]}]
set_property PACKAGE_PIN AK5  [get_ports {DATA[4]}]
set_property PACKAGE_PIN AM1  [get_ports {DATA[5]}]
set_property PACKAGE_PIN AL2  [get_ports {DATA[6]}]
set_property PACKAGE_PIN AK4  [get_ports {DATA[7]}]
set_property PACKAGE_PIN AN1  [get_ports {DATA[8]}]
set_property PACKAGE_PIN AL3  [get_ports {DATA[9]}]
set_property PACKAGE_PIN AK8  [get_ports {DATA[10]}]
set_property PACKAGE_PIN AN2  [get_ports {DATA[11]}]
set_property PACKAGE_PIN AP2  [get_ports {DATA[12]}]
set_property PACKAGE_PIN AL7  [get_ports {DATA[13]}]
set_property PACKAGE_PIN AL5  [get_ports {DATA[14]}]
set_property PACKAGE_PIN AM4  [get_ports {DATA[15]}]
set_property PACKAGE_PIN AN4  [get_ports {DATA[16]}]
set_property PACKAGE_PIN AM5  [get_ports {DATA[17]}]
set_property PACKAGE_PIN AM6  [get_ports {DATA[18]}]
set_property PACKAGE_PIN AN3  [get_ports {DATA[19]}]
set_property PACKAGE_PIN AP3  [get_ports {DATA[20]}]
set_property PACKAGE_PIN AP4  [get_ports {DATA[21]}]
set_property PACKAGE_PIN AP5  [get_ports {DATA[22]}]
set_property PACKAGE_PIN AN6  [get_ports {DATA[23]}]
set_property PACKAGE_PIN AN7  [get_ports {DATA[24]}]
set_property PACKAGE_PIN AP6  [get_ports {DATA[25]}]
set_property PACKAGE_PIN AP7  [get_ports {DATA[26]}]
set_property PACKAGE_PIN AP11 [get_ports {DATA[27]}]
set_property PACKAGE_PIN AP10 [get_ports {DATA[28]}]
set_property PACKAGE_PIN AP9  [get_ports {DATA[29]}]
set_property PACKAGE_PIN AN9  [get_ports {DATA[30]}]
set_property PACKAGE_PIN AP8  [get_ports {DATA[31]}]
set_property IOSTANDARD LVCMOS18 [get_ports {DATA[*]}]

# Bank 66 HP 1.8V
set_property PACKAGE_PIN Y8  [get_ports {CLK2_clk_p[0]}]
set_property IOSTANDARD LVDS [get_ports {CLK2_clk_p[0]}]
create_clock -period 8.000 -name CLK2 [get_ports {CLK2_clk_p[0]}]

# MGT
set_property PACKAGE_PIN L27 [get_ports {CLK4_clk_p}]
set_property PACKAGE_PIN G8  [get_ports {CLK1_clk_p}

• optional chapter separate

• sections for different apps

• optional chapter separate

• sections for linux

• Add "No changes." or "Activate: and add List"

#include <configs/platform-auto.h>
#define CONFIG_SYS_BOOTM_LEN 0xF000000

#define DFU_ALT_INFO_RAM \
                "dfu_ram_info=" \
        "setenv dfu_alt_info " \
        "image.ub ram $netstart 0x1e00000\0" \
        "dfu_ram=run dfu_ram_info && dfu 0 ram 0\0" \
        "thor_ram=run dfu_ram_info && thordown 0 ram 0\0"

#define DFU_ALT_INFO_MMC \
        "dfu_mmc_info=" \
        "set dfu_alt_info " \
        "${kernel_image} fat 0 1\\\\;" \
        "dfu_mmc=run dfu_mmc_info && dfu 0 mmc 0\0" \
        "thor_mmc=run dfu_mmc_info && thordown 0 mmc 0\0"

/*Required for uartless designs */
#ifndef CONFIG_BAUDRATE
#define CONFIG_BAUDRATE 115200
#ifdef CONFIG_DEBUG_UART
#undef CONFIG_DEBUG_UART
#endif
#endif

/*Define CONFIG_ZYNQMP_EEPROM here and its necessaries in u-boot menuconfig if you had EEPROM memory. */
#ifdef CONFIG_ZYNQMP_EEPROM
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN  1
#define CONFIG_CMD_EEPROM
#define CONFIG_ZYNQ_EEPROM_BUS          5
#define CONFIG_ZYNQ_GEM_EEPROM_ADDR     0x54
#define CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET  0x20
#endif

/include/ "system-conf.dtsi"
/ {
};

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};

/* ETH PHY */

&gem0 {
    phy-handle = <&phy0>;
    phy0: phy0@1 {
        device_type = "ethernet-phy";
        reg = <1>;
    };
};



/* USB 2.0 */
 
&dwc3_0 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
};
 
&dwc3_1 {
    status = "okay";
    dr_mode = "host";
    maximum-speed = "high-speed";
    /delete-property/phy-names;
    /delete-property/phys;
    /delete-property/snps,usb3_lpm_capable;
};
 


/* SD*/

&sdhci1 {
    disable-wp;
    no-1-8-v;
};

/* SPI */
// &spi0 {
//     num-cs = <1>;
//     ext_command:spidev@0{
//         compatible="spidev";
//         reg = <0>; //chipselect 0
//         spi-max-frequency= <100000>;
//         spidev-name = "EXT";
//     };
// };
// 

/* I2C */
// &i2c0 {
//     #address-cells = <1>;
//     #size-cells = <0>;
// };

&i2c1{  // TEC0850
    #address-cells = <1>;
    #size-cells = <0>;
    // Instantiate EEPROM driver
    eeprom153: eeprom@53 {
        compatible = "atmel,24c02";
        reg = <0x53>;
    };
    // Instantiate EEPROM driver
    eeprom150: eeprom@50 {
        compatible = "atmel,24c128";
        reg = <0x50>;
    };
    // There is also Clock generator chip
    // Si5345 at address 0x69, but there is
    // no standard driver in Linux kernel yet
};

• Add description for other Software, for example SI CLK Builder ...
• SI5338 and SI5345 also Link to:
  • Si5345
  • Si5338

• Note this list must be only updated, if the document is online on public doc!
• It's semi automatically, so do following
  

  • Add new row below first

  • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

  • Metadata is only used of compatibility of older exports