Page History
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- Power Management
- Reset Management
- FMC JTAG
- LED Control
- FAN Control (FPGA)
- FAN Control (FMC
- I2C MUX
Firmware Revision and supported PCB Revision
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Functional Description
JTAG
CPLD JTAG is always enabledselectable with DIP S1-1. (ON FMC, OFF CPLD).
FMC JTAG is accessible with J9 JTAG Pinheader on PCB REV02 and newer only.
Power
Power sequence on will be executed over 4 States:
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State machine restart power sequencing, if on of the power good signal are lost.
FMC VADJ is set to selectable via DIP S1-2...4.
| S1-4 | S1-3 | S1-2 | Voltage |
|---|---|---|---|
| OFF | OFF | OFF | 3.3V |
| 0 | 0 | 1 | 2.5V |
| 0 | 1 | 0 | 1.9V |
| 0 | 1 | 1 | 1.5V |
| 1 | 0 | 0 | 1.25V |
| 1 | 0 | 1 | 1.2V |
Note on PCB REV01 it's fix 1.8V.
Reset
PROGRAM_B is controlled by push button after power up sequencing is ready.
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Overview
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