Page History
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| Clock Source | Schematic Name | Frequency | Clock Input Destination |
|---|---|---|---|
| SiTime SiT8008BI oscillator, U10 | USB0_RCLK | 52.000000 MHz | USB 2.0 transceiver PHY U9, pin 26 |
| SiTime SiT8008BI oscillator, U13 | ETH_CLK | 25.000000 MHz | Gigabit Ethernet PHY U12, pin 34 |
| SiTime SiT8008BI oscillator, U7 | - | 25.000000 MHz | Quad PLL clock generator U35, pin 3 |
| DSC1123 oscillator, U23 | B505_CLK1 | 150.0000 MHz | PS GT Bank, dedicated for SATA interface |
DSC1123 oscillator, U6 optional, not equipped | B505_CLK0 | 100.0000 MHz | PS GT Bank, dedicated for USB interface |
Silicon Labs 570FBB000290DG, U45 optional, not equipped | B47_L5 (LVDS) | 250.MHz | PL Bank clock capable input pins |
| SiTime SiT8008BI oscillator, U25 | CLK_CPLD | 2524.576000 MHz | System Controller CPLD U35, pin 128 |
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| Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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| v.93 | John Hartfiel |
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| v.89 | Martin Rohrmüller |
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v.88 | John Hartfiel |
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| 2017-11-15 | v.86 | Ali Naseri |
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2017-11-13 | v.82 | Ali Naseri |
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2017-11-13 | v.80 | John Hartfiel |
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| 2017-10-19 | v.79 | Ali Naseri |
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2017-10-18 | v.75 | Ali Naseri |
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2017-08-29 | v.70 | John Hartfiel |
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| 2017-08-28 | v.69 | Ali Naseri |
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