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Template Revision 2.2 - on construction

Design Name always "TE Series Name" + Design name, for example "TE0720 Test Board"


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Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation
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Table of contents

Table of Contents
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Overview

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General Design description
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Zynq Design PS with Linux and  two Ethernet PHYs connected over EMIO and PL.

Key Features

 

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Excerpt
  • PetaLinux
  • SD
  • 2x ETH (Independent MDIO Interface)
  • I2C
  • RTC

Revision History

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Release Notes and Know Issues

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Linux Message: "macb ... .ethernet eth...: unable to generate target frequency: 25000000 Hz"

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Requirements

Software

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Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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Design supports following carriers:

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Additional HW Requirements:

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Content

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For general structure and of the reference design, see Project Delivery

Design Sources

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Additional Sources

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Prebuilt

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<tr> <th>File                                 </th> <th>File-Extension</th>  <th>Description                                                                              </th> </tr>
<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
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        Scroll Table Layout
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        ExampleComment
        12



  • ...


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Table of contents

Table of Contents
outlinetrue

Overview

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Notes :



Zynq Design PS with Linux and  two Ethernet PHYs connected over EMIO and PL.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • PetaLinux
  • SD
  • 2x ETH (Independent MDIO Interface and DP83848 PHY)
  • I2C
  • RTC
  • Special FSBL for QSPI programming

Revision History

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  • add every update file on the download
  • add design changes on description


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DateVivadoProject BuiltAuthorsDescription
2018-12-102018.2
John Hartfiel
  • rework board part files
  • rework petalinux device tree, driver
  • small changes on xdc
2017-10-062017.2TE0728-test_board_noprebuilt-vivado_2017.2-build_03_20171006103655.zip
TE0728-test_board-vivado_2017.2-build_03_20171006103634.zip
John Hartfiel
  • initial release


Release Notes and Know Issues

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  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if  issue fixed



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titleKnown Issues

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IssuesDescriptionWorkaroundTo be fixed version
Wrong UBoot ETH PHY AddressPHY Address is not set correctly for UBoot------

Linux Message: "macb ... .ethernet eth...: unable to generate target frequency: 25000000 Hz"

This can be ignored, ETH works.------


Requirements

Software

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Notes :

  • list of software which was used to generate the design


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titleSoftware

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SoftwareVersionNote
Vivado2018.2needed
SDK2018.2needed
PetaLinux2018.2needed



Hardware

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Notes :

  • list of software which was used to generate the design

Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

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titleHardware Modules

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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashOthersNotes
TE0728-03-1Q03_1qREV01, REV02, REV03512MB16MB

TE0728-04-1Q04_1qREV04512MB16MB
























Design supports following carriers:

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titleHardware Carrier

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Carrier ModelNotes
TEB0728



Additional HW Requirements:

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titleAdditional Hardware

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Additional HardwareNotes
USB Cable for JTAG/UART
XMOD Programmer


Content

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  • content of the zip file


For general structure and of the reference design, see Project Delivery

Design Sources

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TypeLocationNotes
Vivado<design name>/block_design
<design name>/constraints
<design name>/ip_lib
Vivado Project will be generated by TE Scripts
SDK/HSI<design name>/sw_libAdditional Software Template for SDK/HSI and apps_list.csv with settings for HSI
PetaLinux<design name>/os/petalinuxPetaLinux template with current configuration



Additional Sources

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init.sh<design name>/sd/Additional Initialization Script for Linux



Prebuilt

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  • prebuilt files
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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems




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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Specification-Files*.hdfExported Vivado Hardware Specification for SDK/HSI and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

...

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  • Important set new Vivado version link on every Design update of new vivado version!
  • Set Link to download folder (Remove ../de/.. ../en/.. from url) for example: https://shop.trenz-electronic.de/
en/TE080320171/Starterkit   -->


Reference Design is available on:

Design Flow

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  • Basic Design Steps

  • Add/ Remove project specific description



Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

MIO Bank 501 Power is Carrier depends and set to 3.3V. Please check Settings, if you use a own carrier.

...

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinuxNote: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

Launch

Programming

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Note
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Note:

  • Programming and Startup procedure



Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Not used on this Example.

SD

...

Optional for Boot.bin on QSPI Flash and image.ub

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on SD

...

  • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt

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  • Depends on Carrier, see carrier TRM.

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JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

...

.

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
  3. Type on Vivado TCL Console: TE::pr_program_flash_binfile -swapp u-boot
    Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
             optional "TE::pr_program_flash_binfile -swapp hello_te0728" possible
  4. Copy image.ub on SD-Card
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  5. Insert SD-Card

SD

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section 43680477
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root
  3. You can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. ETH0 works with udhcpc
    3. ETH1 must be configured manually
      1. ifconfig eth1 up
      2. ifconfig eth1 <ip>
        Note for Ping test disable ETH0
    4. RTC check: dmesg | grep rtc

 

System Design - Vivado

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PS Interfaces

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Constrains

Basic module constrains

Code Block
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title_i_bitgen_common.xdc
#
# Common bitgen related settings
#

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

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  1. can use Linux shell now.
    1. I2C 0 Bus type: i2cdetect -y -r 0
    2. ETH0 works with udhcpc
    3. ETH1 must be configured manually
      1. ifconfig eth1 up
      2. ifconfig eth1 <ip>
        Note for Ping test disable ETH0
    4. RTC check: dmesg | grep rtc

 

System Design - Vivado

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  • Description of Block Design, Constrains... BD Pictures from Export...


Block Design

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titleBlock Design
Image Added


PS Interfaces

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titlePS Interfaces

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TypeNote
DDR---
QSPIMIO
CAN1MIO
ETH0EMIO
ETH1EMIO
SD0MIO
UART1MIO
I2C0MIO
SPI1MIO
CAN1MIO
GPIOMIO
WDTEMIO
TTC0..1EMIO


 

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
#
# Common bitgen related settings
#

set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

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#############
#ETH0/ETH1
#####
#pwr_down
set_property PACKAGE_PIN L21 [get_ports {PHY_PD[0]}]
set_property PACKAGE_PIN R20 [get_ports {PHY_PD[1]}]
#rst_n
set_property PACKAGE_PIN M15 [get_ports {PHY_RSTN[0]}]
set_property PACKAGE_PIN R16 [get_ports {PHY_RSTN[1]}]
#io standard
set_property IOSTANDARD LVCMOS33 [get_ports {PHY*}]
set_property IOSTANDARD LVCMOS33 [get_ports MDIO_*]
set_property IOSTANDARD LVCMOS33 [get_ports {MII_*}]
#pullup/down for PHY address 1
set_property PULLUP   true [get_ports MII_col]
set_property PULLDOWN true [get_ports {MII_rxd[0]}]
set_property PULLDOWN true [get_ports {MII_rxd[1]}]
set_property PULLDOWN true [get_ports {MII_rxd[2]}]
set_property PULLDOWN true [get_ports {MII_rxd[3]}]
#pullup/down for PHY address 3
set_property PULLUP true [get_ports MII_1_col]
set_property PULLUP true [get_ports {MII_1_rxd[0]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[1]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[2]}]
set_property PULLDOWN true [get_ports {MII_1_rxd[3]}]

#############
#ETH0
#####
set_property PACKAGE_PIN M16 [get_ports MDIO_ETHERNET_0_mdio_io]
set_property PACKAGE_PIN P16 [get_ports MDIO_ETHERNET_0_mdc]
set_property PACKAGE_PIN M22 [get_ports {MII_txd[3]}]
set_property PACKAGE_PIN K21 [get_ports {MII_txd[2]}]
set_property PACKAGE_PIN M17 [get_ports {MII_txd[1]}]
set_property PACKAGE_PIN J22 [get_ports {MII_txd[0]}]
set_property PACKAGE_PIN J20 [get_ports {MII_rxd[3]}]
set_property PACKAGE_PIN J18 [get_ports {MII_rxd[2]}]
set_property PACKAGE_PIN K18 [get_ports {MII_rxd[1]}]
set_property PACKAGE_PIN L17 [get_ports {MII_rxd[0]}]
set_property PACKAGE_PIN L16 [get_ports MII_col]
set_property PACKAGE_PIN N15 [get_ports MII_crs]
set_property PACKAGE_PIN L21L18 [get_ports {PHY_PD[0]}MII_rx_clk]
set_property PACKAGE_PIN R20P15 [get_ports {PHY_PD[1]}]
#rst_n
MII_rx_dv]
set_property PACKAGE_PIN M15P17 [get_ports {PHY_RSTN[0]}]MII_rx_er]
set_property PACKAGE_PIN R16K19 [get_ports {PHY_RSTN[1]}]
#io standardMII_tx_clk]
set_property IOSTANDARDPACKAGE_PIN LVCMOS33J21 [get_ports {PHY*}]
MII_tx_en]

#############
#ETH1
#####
set_property IOSTANDARDPACKAGE_PIN LVCMOS33T16 [get_ports MDIO_ETHERNET_1_mdio_*io]
set_property IOSTANDARDPACKAGE_PIN LVCMOS33T17 [get_ports MDIO_*ETHERNET_1_mdc]
set_property IOSTANDARDPACKAGE_PIN LVCMOS33R21 [get_ports {MII_*}]
#pullup/down for PHY address 11_txd[3]}]
set_property PULLUPPACKAGE_PIN  P22 true [get_ports {MII_col1_txd[2]}]
set_property PULLDOWNPACKAGE_PIN trueP21 [get_ports {MII_rxd1_txd[01]}]
set_property PULLDOWNPACKAGE_PIN trueN22 [get_ports {MII_rxd1_txd[10]}]
set_property PULLDOWNPACKAGE_PIN trueT19 [get_ports {MII_1_rxd[23]}]
set_property PULLDOWNPACKAGE_PIN trueT18 [get_ports {MII_1_rxd[32]}]
#pullup/down for PHY address 2
set_property PULLDOWNPACKAGE_PIN trueR19 [get_ports {MII_1_colrxd[1]}]
set_property PULLUP   truePACKAGE_PIN R18 [get_ports {MII_1_rxd[0]}]
set_property PULLDOWNPACKAGE_PIN trueP20 [get_ports {MII_1_rxd[1]}col]
set_property PULLDOWNPACKAGE_PIN trueN18 [get_ports {MII_1_rxd[2crs]}]
set_property PULLDOWNPACKAGE_PIN trueM19 [get_ports {MII_1_rxd[3]}]

#############
#ETH0
#####
rx_clk]
set_property PACKAGE_PIN M16N17 [get_ports mdioMII_ethernet1_0rx_mdio_iodv]
set_property PACKAGE_PIN P16P18 [get_ports MDIOMII_ETHERNET1_0rx_mdcer]
set_property PACKAGE_PIN M22N19 [get_ports {MII_txd[3]}]_1_tx_clk]
set_property PACKAGE_PIN K21M21 [get_ports {MII_txd[2]}]
set_property PACKAGE_PIN M17 [get_ports {MII_txd[1]}]
set_property PACKAGE_PIN J22 [get_ports {MII_txd[0]}]
set_property PACKAGE_PIN J20 [get_ports {MII_rxd[3]}]
set_property PACKAGE_PIN J18 [get_ports {MII_rxd[2]}]
set_property PACKAGE_PIN K18 [get_ports {MII_rxd[1]}]
set_property PACKAGE_PIN L17 [get_ports {MII_rxd[0]}]
set_property PACKAGE_PIN L16 [get_ports MII_col]
set_property PACKAGE_PIN N15 [get_ports MII_crs]
set_property PACKAGE_PIN L18 [get_ports MII_rx_clk]
set_property PACKAGE_PIN P15 [get_ports MII_rx_dv]
set_property PACKAGE_PIN P17 [get_ports MII_rx_er]
set_property PACKAGE_PIN K19 [get_ports MII_tx_clk]
set_property PACKAGE_PIN J21 [get_ports MII_tx_en]

#############
#ETH1
#####
set_property PACKAGE_PIN T16 [get_ports mdio_ethernet_1_mdio_io]
set_property PACKAGE_PIN T17 [get_ports MDIO_ETHERNET_1_mdc]
set_property PACKAGE_PIN R21 [get_ports {MII_1_txd[3]}]
set_property PACKAGE_PIN P22 [get_ports {MII_1_txd[2]}]
set_property PACKAGE_PIN P21 [get_ports {MII_1_txd[1]}]
set_property PACKAGE_PIN N22 [get_ports {MII_1_txd[0]}]
set_property PACKAGE_PIN T19 [get_ports {MII_1_rxd[3]}]
set_property PACKAGE_PIN T18 [get_ports {MII_1_rxd[2]}]
set_property PACKAGE_PIN R19 [get_ports {MII_1_rxd[1]}]
set_property PACKAGE_PIN R18 [get_ports {MII_1_rxd[0]}]
set_property PACKAGE_PIN P20 [get_ports MII_1_col]
set_property PACKAGE_PIN N18 [get_ports MII_1_crs]
set_property PACKAGE_PIN M19 [get_ports MII_1_rx_clk]
set_property PACKAGE_PIN N17 [get_ports MII_1_rx_dv]
set_property PACKAGE_PIN P18 [get_ports MII_1_rx_er]
set_property PACKAGE_PIN N19 [get_ports MII_1_tx_clk]
set_property PACKAGE_PIN M21 [get_ports MII_1_tx_en]

Software Design - SDK/HSI

HTML
<!--
optional chapter
separate sections for different apps
  -->

For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

Xilinx default FSBL

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

HTML
<!--
optional chapter
  -->

Description currently not available.

Config

No changes.

U-Boot

No changes.

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* ETH PHY */
&gem0 {
    phy-mode = "mii";
    status = "okay"1_tx_en]

Software Design - SDK/HSI

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Note:
  • optional chapter separate

  • sections for linux

  • Add "No changes." or "Activate: and add List"


For SDK project creation, follow instructions from:

SDK Projects

Application

Template location: ./sw_lib/sw_apps/

zynq_fsbl

TE modified 2018.2 FSBL

Xilinx default FSBL,

Changes::

  • only active FSBL banner independence form debug flags

zynq_fsbl_flash

TE modified 2018.2 FSBL

FSBL(for Vivado/SDK GUI only) to initialise Zynq for QSPI programming

Changes:

  • Set FSBL Boot Mode to JTAG
  • Disable Memory initialisation
  • see  xfsbl_initialisation.main.c

u-boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

HTML
<!--
optional chapter
  -->

Description currently not available.

Config

No changes.

U-Boot

No changes.

Device Tree

Code Block
languagejs
/include/ "system-conf.dtsi"
/ {
};

/* QSPI PHY */
&qspi {
    #address-cells = <1>;
    #size-cells = <0>;
    status = "okay";
    flash0: flash@0 {
        compatible = "jedec,spi-nor";
        reg = <0x0>;
        #address-cells = <1>;
        #size-cells = <1>;
    };
};


/* ETH PHY */

&gem0{ 
    status = "okay";
    phy-mode = "mii";
    phy-handle = <&phy1>; 
    xlnx,has-mdio = <0x1>; 
    mdio { 
        #address-cells = <1>; 
        #size-cells = <0>; 
        phy1: phy@1 { 
            device_type = "ethernet-phy"; 
            compatible = "ethernet-phy-id2000.5C90";
        max-speed = <0x64>;
        ethernet_phy0: ethernet-phy@0 {
       reg = <1>; 
     // compatible = "marvell,88e1510"}; 
    }; 
}; 


&gem1{  device_type
    status = "ethernet-phyokay";
    phy-mode = "mii";
    phy-handle = <&phy3>; 
   reg xlnx,has-mdio = <1><0x1>; 
    };
};

&gem1mdio { 
    phy-mode = "mii";
    status#address-cells = "okay"<1>; 
    local-mac-address = [00 0a 35 00 1e 01]; #size-cells = <0>; 
        ethernet_phy1phy3: ethernet-phy@1phy@3 { 
        // compatible    device_type = "marvell,88e1510ethernet-phy"; 
        device_typecompatible = "ethernet-phy-id2000.5C90";
        max-speed = <0x64>;
            reg = <2>; <3>; 
        }; 
    }; 
}; 


/* RTC */

&i2c0 {
    rtc@56 {        // Real Time Clock
       compatible = "rv3029c2";
       reg = <0x56>;
   };
 
};





Kernel

Activate:

  • RTC_DRV_RV3029C2
  • DP83848_RV3029C2PHY

Rootfs

Activate:

  • I2C-tools

Applications

...

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

...

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:


No additional software is needed.

...

DateDocument RevisionAuthorsDescription

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
current-version
current-version
prefixv.


 

Page info
modified-user
modified-user

  • Release 2018.2  (working in process)
  • Design and Documentation is changed

v.10John Hartfiel
  • Release 2017.

  • 2

2017-09-11v.1

Page info
created-user
created-user

  • Initial release
 All

Page info
modified-users
modified-users

 

...