Page History

Custom_table_size_100

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Module: TRM Name always "TE Series Name" +TRM
Example: "TE0728 TRM"

Template Change history:

Version	Changes	Author
4.0	Rework for smaller TRM which can be generated faster Reduce Signal Interfaces Pin Reduce On Board Perihery Reduce Power Move Configuration Signals from Overview to own section	JH
3.12	Version History changed from list to table all changed title-alignment for tables from left to center	ma
3.11	update "Recommended Operating Conditions" section
3.1	New general notes for temperature range to "Recommended Operating Conditions"
3.02	add again fix table of content with workaround to use it for pdf and wiki Export Link for key features examples Notes for different Types (with and without Main FPGA) Export Link for Signals, Interfaces and Pins examples Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
3.01	remove fix table of content and page layout ( split page layout make trouble with pdf export) changed and add note to signal and interfaces, to on board periphery section ...(not finished)
3.00	→ separation of Carrier/Module and evaluation kit TRM
2.15	add excerpt macro to key features
2.14	add fix table of content add table size as macro

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Important General Note:

If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

Figure template:

Scroll Title

anchor	Figure_anchorname
title-alignment	center
title	Text

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Table template:
- Layout macro can be use for landscape of large tables

Scroll Title

anchor	Table_tablename
title-alignment	center
title	Text

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Example	Comment
1	2

The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below
- <type>_<main section>_<name>
  - type: Figure, Table
  - main section:
    - "OV" for Overview
    - "SIP" for Signal Interfaces and Pins,
    - "OBP" for On board Peripherals,
    - "PWR" for Power and Power-On Sequence,
    - "B2B" for Board to Board Connector,
    - "TS" for Technical Specification
    - "VCP" for Variants Currently in Production
    - "RH" for Revision History
  - name: custom, some fix names, see below
- Fix names:
  - "Figure_OV_BD" for Block Diagram
  - "Figure_OV_MC" for Main Components
  - "Table_OV_IDS" for Initial Delivery State
  - "Table_PWR_PC" for Power Consumption
  - "Figure_PWR_PD" for Power Distribution
  - "Figure_PWR_PS" for Power Sequence
  - "Figure_PWR_PM" for Power Monitoring
  - "Table_PWR_PR" for Power Rails
  - "Table_PWR_BV" for Bank Voltages
  - "Table_TS_AMR" for Absolute_Maximum_Ratings
  - "Table_TS_ROC" for Recommended_Operating_Conditions
  - "Figure_TS_PD" for Physical_Dimensions
  - "Table_VCP_SO" for TE_Shop_Overview
  - "Table_RH_HRH" for Hardware_Revision_History
  - "Figure_RH_HRN" for Hardware_Revision_Number
  - "Table_RH_DCH" for Document_Change_History
Use Anchor in the document: add link macro and add "#<anchorname>
Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>

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-----------------------------------------------------------------------

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Note for Download Link of the Scroll ignore macro:

Link to the base folder of the module (remove de/ or en/ from the URL):
Example: https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5_Carriers/TE0728/

Scroll Ignore
Download PDF version of this document.

Overview

The Trenz Electronic TE0xxx-xx ... is an industrial/extended grade ... module ... based on Xilinx/Intel...AMB0010 is a commercial grade baseboard for Andromeda modules.

Refer to http://trenz.org/tec0850amb0010-info for the current online version of this manual and other available documentation.

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Notes :

short description of the PCB
Short Link of the wiki resources reference:
- Use short link the Wiki Resource page, for example: http://trenz.org/te0728-info
- List of available short links: https://wiki.trenz-electronic.de/display/CON/Redirects

Key Features

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Note:
'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures

Excerpt

Module
- Andromeda modules (like AM0010,
SoC/FPGA
- ...
RAM/Storage
- ...
- )
On Board
- ...
Interface
- ...
Power
- ...
Dimension
- ...
- 2 x B2B connector (ADF6)
- Clock Buffer
- Oscillator
Interface
- RJ45 LAN Socket
- XMOD
- UART Header
- I2C Header
- 4 x User DIP Switch
- 4 x User LED
- Micro SD Card Socket with ESD protection
- USB Connector
- Loopbacks for GTHs, IOs, GPIOs
Power
- 12 V Input Supply Voltage
Dimension
- 128 mm x 106 mm
Notes
- ...

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .

Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram

Note

All created DrawIOs should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD

Scroll Title

anchor	Figure_OV_BD
title-alignment	center
title	TExxxx AMB0010 block diagram

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Main Components

draw.io Diagram

border	true

diagramName	AMB0010_OV_BD
simpleViewer	true
width
links	auto
tbstyle	top
diagramDisplayName
lbox	true
diagramWidth	721
revision	4

Scroll Only
Image Added

Main Components

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Notes :

Picture of the

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Notes :

Picture of the PCB (top and bottom side) with labels of important components
Add List below

Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .

Scroll Title

anchor	Figure_OV_MC
title-alignment	center
title	TExxxx AMB0010 main components

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

...
...
...

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

draw.io Diagram

border	true

diagramName	Figure_OV_MC
simpleViewer	true
width
links	auto
tbstyle	top
diagramDisplayName
lbox	true
diagramWidth	1201
revision	2

Scroll Only
Image Added

B2B Connector (ADF6), JB5, JB6
Power Jack, J1
Push Button, S1, S3, S4
DIP Switch, S2, S5
LED, D3...9
Pin Header, J8, J19
ESD Protection, U13
Micro SD Socket, J13
XMOD Connector, JB1
RJ45 LAN Socket, J11
USB Socket, J12

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Storage device name	Content	Notes
-	-	-

Signals

Scroll Title

anchor	Table_OV_IDS
title-alignment	center
title	Initial delivery state of programmable devices on the module

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

Storage device name

Content

Notes

Quad SPI Flash

EEPROMSystem Controller CPLDDDR4 SDRAMeMMCProgrammable Clock Generator

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note
Table with all connectors and Designtor List of different interfaces per connector IO CNT (for FPGA IOs where functionality can be changed by customer)

Connectors

Scroll Title

anchor	Table_SIP_C
title-alignment	center
title	Board Connectors

Scroll Table Layout

orientation	portrait
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cellHighlighting	true

Connector Type	Designator	Interface	IO CNT	Notes

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

B2B	JB5	HP	104 SE / 48 DIFF	Loopbacked.
B2B	JB5	MGT PL	4 x MGT (RX/TX)	Loopbacked.
B2B	JB5	MGT PL	2 x MGT CLK
B2B	JB5	HD	24 SE / 12 DIFF	Loopbacked.
B2B	JB6	HP	52 SE / 24 DIFF	Loopbacked.
B2B	JB6	MGT PS	4 x MGT (RX/TX)	Not connected.
B2B	JB6	MGT PS	2 x MGT CLK
B2B	JB6	HD	24 SE / 12 DIFF	Loopbacked.
B2B	JB6	MIO	2 x I2C
B2B	JB6	MIO	2 x UART
B2B	JB6	MIO	2 x PERST	Loopbacked.
B2B	JB6	MIO	SDIO
B2B	JB6	MIO	JTAG
B2B	JB6	MIO	4 x GPIO	Loopbacked.
B2B	JB6	ETH
B2B	JB6	USB
RJ45	J11	ETH
XMOD	JB1	JTAG	JTAG
XMOD	JB1	UART	UART
Pin Header	J8	UART	UART
Pin Header	J19	I2C	I2C
Power Jack	J1	PWR	PWR
SD Card Socket	J13	SDIO	SDIO
USB Socket	J12	USB	USB

Test Points

Test PointSignalB2BNotes10PWR_PL_OKJ2-120 Scroll Title

anchor	Table_SIP_TPs
title-alignment	center
title	Test Points Information

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueTest PointSignalConnected toNotesTP1

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/InterfaceDesignatorConnected ToNotesETH PHYU10

B2B connector J1
SoC MIO

Gigabit ETH PHY Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueChip/InterfaceDesignatorConnected ToNotes

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id	Comments

For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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id Comments
you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.
Example:
Test Point Signal B2B Notes
10 PWR_PL_OK J2-120

Scroll Title
anchor Table_SIP_TPs
title-alignment center
title Test Points Information
Scroll Table Layout
orientation portrait
sortDirection ASC
repeatTableHeaders default
style
widths
sortByColumn 1
sortEnabled false
cellHighlighting true
Test Point Signal Notes¹⁾
TP1 +12.0V_input
TP2 +12.0V_input
TP3 V_MOD1 OUT
TP4 V_MOD1 OUT
TP5 Carrier_+3V3 OUT
TP6 Carrier_+3V3 OUT
TP7 Carrier_+1V8 OUT
TP8 Carrier_+1V8 OUT
TP9 Module_+3.3V Connected to JB6, U4 - IN
TP10 Module_+3.3V Connected to JB6, U4 - IN
TP11 Module_+1.8V Connected to JB5, JB6 - IN
TP12 Module_+1.8V Connected to JB5, JB6 - IN
TP13 PWR_EN JB6, S4 - PWR_EN is pulled-up in module AM0010 to 3.3 V.
TP14 PWR_EN JB6, S4 - PWR_EN is pulled-up in module AM0010 to 3.3 V.
TP15 Carrier_USB+5V
TP16 Carrier_USB+5V
TP17 PG_Carrier_+1V8 Connected to U2, U3, U4, U5, U6, U7, U12
TP18 PG_Carrier_+1V8 Connected to U2, U3, U4, U5, U6, U7, U12
TP19 Carrier_PG Connected to U3, U6, T7 (LED D5)
TP20 Carrier_PG Connected to U3, U6, T7 (LED D5)
TP21 PG_Carrier_USB+5V Connected to U7, U12
TP22 PG_Carrier_USB+5V Connected to U7, U12
TP23 PWR_GOOD Connected to JB6, U4 - IN (M2C), pulled-up in module AM0010 to 3.3 V.
TP24 PWR_GOOD Connected to JB6, U4 - IN (M2C), pulled-up in module AM0010 to 3.3 V.
TP25 USB-VBUS
TP26 USB-VBUS
TP27 IO_X0_D12_P Connected to JB6
TP28 IO_X0_D12_P Connected to JB6
TP29 M_SDA Connected to JB6
TP30 M_SDA Connected to JB6
TP31 M_SCL Connected to JB6
TP32 M_SCL Connected to JB6
TP33 RST_M2C# Connected to JB6
TP34 RST_M2C# Connected to JB6
TP35 U_INT Connected to JB6
TP36 U_INT Connected to JB6
TP37 PS_POR# Connected to JB6, S3 - PS_POR# is pulled up in module AM0010 to Carrier_+3V3 (V_IO_CFG).
TP38 PS_POR# Connected to JB6, S3 - PS_POR# is pulled up in module AM0010 to Carrier_+3V3 (V_IO_CFG).
TP39 PS_SRST# Connected to JB6, S1 - PS_SRST# is pulled up in module AM0010 to Carrier_+3V3 (V_IO_CFG).
TP40 PS_SRST# Connected to JB6, S1 - PS_SRST# is pulled up in module AM0010 to Carrier_+3V3 (V_IO_CFG).
TP41 DX_P Connected to JB6
TP42 DX_P Connected to JB6
TP43 DX_N Connected to JB6
TP44 DX_N Connected to JB6
TP45 M_INT Connected to JB6
TP46 M_INT Connected to JB6
¹⁾ Direction:
IN: Input from the point of view of this board.
OUT: Output from the point of view of this board.

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example:

Chip/Interface	Designator	Connected To	Notes
ETH PHY	U10	B2B connector J1 SoC MIO	Gigabit ETH PHY

Scroll Title

anchor	Table_OBP
title-alignment	center
title	On board peripherals

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Chip/Interface	Designator	Connected To	Notes
Oscillator	U10	U11	100 MHz
Clock Buffer	U11	JB5
RJ45 LAN Socket	J11	JB6
XMOD	JB1	JB6
Pin Header	J8	JB6
Pin Header	J19	JB6
Power Jack	J1
Micro SD Card Socket	J13	JB6 via U13
USB Socket	J12	JB6 via L7

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

Configuration and System Control Signals

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Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...
In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OV_CNTRL
title-alignment	center
title	Controller signal.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector.Pin	Signal Name	Direction¹⁾	Description
JB6.A59	V_BAT	OUT	Input voltage for VCC_PSBATT ^{2) 3)}.
JB6.B58	RST_M2C#	IN	Module reset for peripheral reset
JB6.C53	DONE	IN	Signal PS_DONE.
JB6.C54 / JB6.C55 / JB6.C56 / JB6.C57	MODE0...3	OUT	Boot mode selection. Consider possible module boot modes.
JB6.C58	PS_SRST#	OUT	FPGA system reset ^{2) 3)}.
JB6.C59	PS_POR#	OUT	Power-on-reset status ^{2) 3)}.
JB6.D56 / JB6.D57	DX_P / DX_N	OUT	Temperature sensing diode pin
JB6.D58	PWR_EN	OUT	Power Enable ^{2) 3)}. Controlled module internally. Can be used to delay power on sequencing or disable power. Tie only to GND or leave floating.
JB6.D59	PWR_GOOD	IN	Power good status
J6.D51 / J6.D52 / J6.D54 / J6.D55	TDI/TCK/TDO/TMS	Signal-dependent	JTAG configuration and debugging interface ^{2) 3)}. JTAG reference voltage: 3.3 V

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

²⁾ See UG1085 for additional information.

³⁾ Consider modules input voltage range.

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power

Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Connector + Pin	Direction¹⁾
V_MOD1	JB5.A7 / JB5.A15 / JB5.A47 / JB5.A55 / JB5.B5 / JB5.B11 / JB5.B17 / JB5.B45 / JB5.B51 / JB5.B57 / JB6.C5 / JB6.C11 / JB6.C17 / JB6.D7 / JB6.D15	OUT
Module_+1.8V	J5.C7 / J5.C15 / J6.B7 / J6.B15	IN
Carrier_+1V8	JB5.D3 / JB5.D17 / JB5.D43 / JB5.D57 / JB6.A3 / JB6.A17 / JB6.A59	OUT
Carrier_+3V3	JB5.D40 / JB6.B35 / JB6.C52 / JB1.5 / JB1.6 / J8.1 / J19.1	OUT
Module_+3.3V	JB6.B59	IN
+12.0V_input	J1.1	IN

¹⁾ Direction:

- IN: Input from the point of view of this board.
- OUT: Output from the point of view of this board.

Recommended Power up Sequencing (preliminary)

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hidden	true
id	Comments

List baseboard design hints for final baseboard development.

Overview all Controller signals, like Reset, Boote Mode, JTAG Interface(Connector or USB In case of FTDI)...

In case it's connected to CPLD always link to CPLD description and add not from the current implementation here(in case it's available)

Scroll Title

anchor	Table_OVBB_CNTRLDH
title-alignment	center
title	Controller signal.Baseboard Design Hints

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Connector+Pin

Signal Name

Direction

Description

Power and Power-On Sequence

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Enter the default value for power supply and startup of the module here.

Order of power provided Voltages and Reset/Enable signals

Link to Schematics, for power images or more details

Power Rails

List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power

Notes


cellHighlighting	true

Sequence	Net name	Recommended Voltage Range	Pull-up/down	Description	Notes
0	-	-	-	Configuration signal setup.	See Configuration and System Control Signals.
1 ¹⁾	V_BAT	3.3 V	-	Battery connection.	Battery Power Domain usage. When not used, tie to GND.
2	V_MOD1	12 V	-	Main Power supply.	Main module power supply. 3 A recommended. Power consumption depends mainly on design and cooling solution.
3 ¹⁾	PWR_EN	-	PU ²⁾, 3.3 V	Power release.	Controlled module internally. Can be used to delay power on sequencing or disable power. Tie only to GND or leave floating.
4	PWR_GOOD	-	PU ²⁾, 3.3 V	Power good status.	Module power on sequencing finished. Periphery and variable bank voltages can be enabled on carrier.
5 ¹⁾	3.3V / 1.8V	-	-	Module generated output voltages.	Voltages are available after PWR_GOOD deassertion. These voltages can be used to supply bank voltages, to supply periphery and/or as power good signal to enable external power regulators. Important: Consider maximum power consumption.
5	V_IO_W01 / V_IO_W45 / V_IO_X01 / V_IO_W3 / V_IO_X3 / V_IO_CFG	³⁾	-	Module bank voltages.	Enable bank voltages after PWR_GOOD deassertion.
6 ¹⁾	-	-	-	Reset handling.	RST_M2C# delivers external periphery reset. See Configuration and System Control Signals.

¹⁾ (optional)

²⁾ (on module)

³⁾ See DS925 for additional information.

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Scroll Title

anchor	Table_PWR_PR
title-alignment	center
title	Module power rails.

Scroll Table Layout

orientation

portrait

sortDirection

ASC

repeatTableHeaders

default

style

widths

sortByColumn

1

sortEnabled

false

cellHighlighting

true

Power Rail Name/ Schematic Name

Connector + Pin

Direction

Board to Board Connectors

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id	Comments

This section is optional and only for modules.
use "include page" macro and link to the general B2B connector page of the module series,
For example: 6 x 6 SoM LSHM B2B Connectors
Include Page
PD:6 x 6 SoM LSHM B2B ConnectorsPD:
6 x 6 SoM LSHM B2B Connectors

Include Page

	Andromeda ADM6/ADF6 B2B Connectors
	Andromeda ADM6/ADF6 B2B Connectors

Technical Specifications

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List of all Powerrails which are accessible by the customer

Main Power Rails and Variable Bank Power add boarder one time maximum Rating (Board will damaged)

Absolute Maximum Ratings

Scroll Title

anchor	Table_TS_AMR
title-alignment	center
title	PS absolute Absolute maximum ratings

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/

Schematic Name

Description

Min

Max

Unit

V

°C

Schematic Name	Description	Min	Max	Unit
+12.0V_input	Power Supply	11.0	13.0	V
Module_+3.3V	Input from Module	3.315	3.465	V
Module_+1.8V	Input from Module	1.71	1.89	V

Recommended Operating Conditions

This TRM is generic for all variants. Temperature range can be differ depending on the assembly version. Voltage range is mostly the same during variants (exceptions are possible, depending on custom request)

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Variants of modules are described here: Article Number Information
Modules with commercial temperature grade are equipped with components that cover at least the range of 0°C to 75°C
Modules with extended temperature grade are equipped with components that cover at least the range of 0°C to 85°C
Modules with industrial temperature grade are equipped with components that cover at least the range of -40°C to 85°C
The actual operating temperature range will depend on the FPGA / SoC design / usage and cooling and other variables.

Scroll Title

anchor	Table_TS_ROC
title-alignment	center
title	Recommended operating conditions.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
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sortByColumn	1
sortEnabled	false
cellHighlighting	true

Power Rail Name/ Schematic Name	Min	Typical	Max	Units	Reference Document	V	See ???? datasheets.	V	See ???? datasheet.	V	See ???? datasheet.	V	See ???? datasheet.	V	See ???? datasheet.	V	See ???? datasheet.	V	See ???? datasheet.	°C	See ???? datasheet.
+12.0V_input	11.0	12.0	13.0	V	See LTC4365ITS8 datasheets.
Module_+3.3V	3.315	3.3	3.465	V
Module_+1.8V	1.71	1.8	1.89	V

Physical Dimensions

Module size: ?? 128 mm × ?? 106 mm. Please download the assembly diagram for exact numbers.
Mating height with standard connectors: ? 5 mm.

PCB thickness: ?? 1.6 mm.

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id	Comments

In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" ." .

Scroll Title

anchor	Figure_TS_PD
title-alignment	center
title	Physical Dimension

Scroll Ignore

draw.io Diagram

border	true

diagramName	Figure_TS_PD
simpleViewer	true
width
links	auto
tbstyle	top
diagramDisplayName
lbox	true
diagramWidth	1060
revision	2

Scroll Title

anchor	Figure_TS_PD
title-alignment	center
title	Physical Dimension

Scroll Ignore

Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only

scroll-pdf	true
scroll-office	true
scroll-chm	true
scroll-docbook	true
scroll-eclipsehelp	true	scroll-epub	true
scroll-html	true	-epub	true
scroll-html	true

Image Addedimage link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Currently Offered Variants

Page properties

hidden	true
id	Comments

Set correct link to the shop page overview table of the product on English and German.

Example for TE0706:

ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

Scroll Title

anchor	Table_VCP_SO
title-alignment	center
title	Trenz Electronic Shop Overview

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Trenz shop TEXXXX AMB0010 overview page
English page	German page

Revision History

Hardware Revision History

Page properties

hidden	true
id	Comments

Set correct links to download Carrier, e.g. TE0706 REV02:

TE0706-02 -> https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

Date format: YYYY-MM-DD
Example:
Date Revision Changes Documentation Link
2020-11-25 REV02
Resistors R14 and R15 was replaced by 953R (was 5K1)
Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
REV02

Scroll Title

anchor	Figure_RV_HRN
title-alignment	center
title	Board hardware revision number.

title-alignment	center
title	Board hardware revision number.

Scroll Ignore

draw.io Diagram

border	true

diagramName	Figure_RV_HRN
simpleViewer	true
width
links	auto
tbstyle	top
diagramDisplayName
lbox	true
diagramWidth	246
revision	1

Scroll Only
Image Added

Scroll Ignore
Create DrawIO object here: Attention if you copy from other page, objects are only linked.

Scroll Only
image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed

Scroll Title

anchor	Table_RH_HRH
title-alignment	center
title	Hardware Revision History

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date	Revision	Changes	Documentation Link
-	REV01	Initial Revision

Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Document Change History

Page properties

hidden	true
id	Comments

Note this list must be only updated, if the document is online on public doc!
It's semi automatically, so do following
- Add new row below first
- Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template
- Metadata is only used of compatibility of older exports

Scroll Title

anchor	Table_RH_DCH
title-alignment	center
title	Document change history.

Scroll Table Layout

orientation	portrait
sortDirection	ASC
repeatTableHeaders	default
style
widths
sortByColumn	1
sortEnabled	false
cellHighlighting	true

Date

Revision

Contributor

Description

Page info

infoType	Modified date
dateFormat	yyyy-MM-dd
type	Flat

Page info

infoType	Current version
prefix	v.
type	Flat
showVersions	false

Page info

infoType	Modified by
type	Flat
showVersions	false

<add TRM change list here>Initial Document

--

all

Page info

infoType	Modified users
type	Flat
showVersions	false

--

Disclaimer

Include Page

	IN:Legal Notices
	IN:Legal Notices

Scroll Only

HTML
<style> .wiki-content .columnLayout .cell.aside { width: 0%; }</style>

Scroll pdf ignore

Custom_fix_page_content

Trenz Electronic Documentation

Page History

Versions Compared

Old Version 1

New Version Current

Key

Overview

Key Features

Block Diagram

Main Components

Main Components

Initial Delivery State

Initial Delivery State

Signals

Signals, Interfaces and Pins

Connectors

Test Points

Test Points

On-board Peripherals

On-board Peripherals

Oscillator

Clock Buffer

RJ45 LAN Socket

XMOD

Pin Header

Power Jack

Micro SD Card Socket

USB Socket

Configuration and System Control Signals

Power and Power-On Sequence

Power Rails

Recommended Power up Sequencing (preliminary)

Power and Power-On Sequence

Power Rails

Board to Board Connectors

Technical Specifications

Absolute Maximum Ratings

Recommended Operating Conditions

Physical Dimensions

Currently Offered Variants

Revision History

Hardware Revision History

Document Change History

Disclaimer

Table of contents