Page History
| Page properties | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
|
| Custom_table_size_100 |
|---|
| Page properties | ||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||
Important General Note:
|
Overview
| Scroll Ignore | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
| Page properties | ||||
|---|---|---|---|---|
| ||||
Notes :
|
Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.
Key Features
| Page properties | ||||
|---|---|---|---|---|
| ||||
Notes :
|
| Excerpt |
|---|
|
Revision History
| Page properties | ||||
|---|---|---|---|---|
| ||||
Notes :
|
| Expand | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Release Notes and Know Issues
| Page properties | ||||
|---|---|---|---|---|
| ||||
Notes :
|
| Scroll Title | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||
|
Requirements
Software
| Page properties | ||||
|---|---|---|---|---|
| ||||
Notes :
|
| Scroll Title | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||
|
Hardware
| Page properties | ||||
|---|---|---|---|---|
| ||||
Notes :
|
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
| Expand | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
Note: Design contains also Board Part Files for TE0808+TEBF0808 configuration, this board part files are not used for this reference design.
Design supports following carriers:
| Scroll Title | ||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||
*used as reference |
Additional HW Requirements:
| Scroll Title | ||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||
*used as reference |
Content
| Page properties | ||||
|---|---|---|---|---|
| ||||
Notes :
|
Design Sources
| Scroll Title | |||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||
|
Additional Sources
| Scroll Title | ||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||
|
Prebuilt
| Page properties | |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| |||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
Notes :
|
| Scroll Title | ||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||
|
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
| Page properties | ||||
|---|---|---|---|---|
| ||||
|
Design Flow
| Scroll Ignore | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
| Page properties | ||||
|---|---|---|---|---|
| ||||
Notes :
|
| Note |
|---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
| Note |
|---|
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block language bash theme Midnight title _create_win_setup.cmd/_create_linux_setup.sh ------------------------Set design paths---------------------------- -- Run Design with: _create_win_setup -- Use Design Path: <absolute project path> -------------------------------------------------------------------- -------------------------TE Reference Design--------------------------- -------------------------------------------------------------------- -- (0) Module selection guide, project creation...prebuilt export... -- (1) Create minimum setup of CMD-Files and exit Batch -- (2) Create maximum setup of CMD-Files and exit Batch -- (3) (internal only) Dev -- (4) (internal only) Prod -- (c) Go to CMD-File Generation (Manual setup) -- (d) Go to Documentation (Web Documentation) -- (g) Install Board Files from Xilinx Board Store (beta) -- (a) Start design with unsupported Vivado Version (beta) -- (x) Exit Batch (nothing is done!) ---- Select (ex.:'0' for module selection guide):- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note Note: Select correct one, see also Vivado Board Part Flow
Important: Use Board Part Files, which did not end with *_tebf0808
Create hardware description file (.xsa file) and export to prebuilt folder
Code Block language py theme Midnight title run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") TE::hw_build_design -export_prebuiltInfo Using Vivado GUI is the same, except file export to prebuilt folder.
Generate Programming Files with Vitis
Code Block language py theme Midnight title run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") TE::sw_run_vitis -all TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)Note TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis
Launch
| Scroll Ignore | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
| Page properties | ||||
|---|---|---|---|---|
| ||||
Note:
|
Programming
| Note |
|---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated
QSPI-Boot mode
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Code Block language bash theme Midnight title run on Vivado TCL (Script programs BOOT.bin on QSPI flash) TE::pr_program_flash -swapp hello_te0808
SD-Boot mode
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with Vitis Debugger into device
Usage
QSPI Boot:
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select QSPI as Boot Mode
Info Note: See TRM of the Carrier, which is used.
Power On PCB
Expand title boot process 1. ZynqMP Boot ROM FSBL from QSPI into OCM,
2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR
System Design - Vivado
| Scroll Ignore | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
| Page properties | ||||
|---|---|---|---|---|
| ||||
Note:
|
Block Design
| Scroll Title | ||||||
|---|---|---|---|---|---|---|
| ||||||
 |
PS Interfaces
| Page properties | ||||
|---|---|---|---|---|
| ||||
Note:
|
| Scroll Title | ||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||
|
Constrains
Basic module constrains
| Code Block | ||||
|---|---|---|---|---|
| ||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Not needed.
Software Design - Vitis
| Scroll Ignore | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
| Page properties | ||||
|---|---|---|---|---|
| ||||
Note:
|
Application
| Page properties | ||||
|---|---|---|---|---|
| ||||
---------------------------------------------------------- FPGA Example ---------------------------------------------------------- scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2023.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions:
xilisf_v5_11TE modified 2023.2 xilisf_v5_11
---------------------------------------------------------- Zynq Example: ---------------------------------------------------------- fsblTE modified 2023.2 FSBL General:
Module Specific:
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2023.2 FSBL General:
Module Specific:
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
zynqmp_fsbl
TE modified 2023.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display FSBL Banner and Device Name
hello_te0808
Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Software
| Scroll Ignore | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
| Page properties | ||||
|---|---|---|---|---|
| ||||
| Note: |
Appx. A: Change History and Legal Notices
| Scroll Ignore | ||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||
Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
| Page properties | ||||
|---|---|---|---|---|
| ||||
|
| Scroll Title | ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
| ||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||||
|
| HTML |
|---|
<!--
Template Revision 1.0
Basic Notes
- export PDF to download, if vivado revision is changed!
- Template is for different design and SDSoC and examples, remove unused or wrong description!
--> |
| Scroll Only (inline) |
|---|
Online version of this manual and other related documents can be found at https://wiki.trenz-electronic.de/display/PD/Trenz+Electronic+Documentation |
| Scroll pdf ignore | ||||
|---|---|---|---|---|
Table of contents
|
Overview
| HTML |
|---|
<!--
General Design description
--> |
Key Features
| HTML |
|---|
<!--
Add Basic Key Features of the design (should be tested)
--> |
| Excerpt |
|---|
|
Revision History
| HTML |
|---|
<!--
- Add changes from design
- Export PDF to download, if vivado revision is changed!
--> |
...
Release Notes and Know Issues
| HTML |
|---|
<!--
- add known Design issues and general Notes for the current revision
--> |
...
Requirements
Software
| HTML |
|---|
<!--
Add needed external Software
--> |
...
Hardware
| HTML |
|---|
<!--
Hardware Support
--> |
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
...
Design supports following carriers:
...
Additional HW Requirements:
...
Content
| HTML |
|---|
<!--
Remove unused content
--> |
For general structure and of the reference design, see Project Delivery
Design Sources
...
Additional Sources
...
Prebuilt
| HTML |
|---|
<!--
<table width="100%">
<tr> <th>File </th> <th>File-Extension</th> <th>Description </th> </tr>
<tr> <td>BIF-File </td> <td>*.bif </td> <td>File with description to generate Bin-File </td> </tr>
<tr> <td>BIN-File </td> <td>*.bin </td> <td>Flash Configuration File with Boot-Image (Zynq-FPGAs) </td> </tr>
<tr> <td>BIT-File </td> <td>*.bit </td> <td>FPGA Configuration File </td> </tr>
<tr> <td>DebugProbes-File </td> <td>*.ltx </td> <td>Definition File for Vivado/Vivado Labtools Debugging Interface </td> </tr>
<tr> <td>Debian SD-Image </td> <td>*.img </td> <td>Debian Image for SD-Card </td> </tr>
<tr> <td>Diverse Reports </td> <td> --- </td> <td>Report files in different formats </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf </td> <td>Exported Vivado Hardware Specification for SDK/HSI </td> </tr>
<tr> <td>LabTools Project-File </td> <td>*.lpr </td> <td>Vivado Labtools Project File </td> </tr>
<tr> <td>MCS-File </td> <td>*.mcs </td> <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) </td> </tr>
<tr> <td>MMI-File </td> <td>*.mmi </td> <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image </td> <td>*.ub </td> <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) </td> </tr>
<tr> <td>Software-Application-File </td> <td>*.elf </td> <td>Software Application for Zynq or MicroBlaze Processor Systems </td> </tr>
<tr> <td>SREC-File </td> <td>*.srec </td> <td>Converted Software Application for MicroBlaze Processor Systems </td> </tr>
</table>
-->
|
...
File
...
File-Extension
...
Description
...
Debian SD-Image
...
*.img
...
Debian Image for SD-Card
...
MCS-File
...
*.mcs
...
Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
...
MMI-File
...
*.mmi
...
File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
...
SREC-File
...
*.srec
...
Converted Software Application for MicroBlaze Processor Systems
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
| HTML |
|---|
<!--
Add correct path:https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803/Reference_Design/2017.1/Starterkit
--> |
Reference Design is available on:
Design Flow
| HTML |
|---|
<!--
Basic Design Steps
Add/ Remove project specific
--> |
| Note |
|---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter for minimum setup
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create HDF and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported HDF
- HDF is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
- Use TE Template from /os/petalinux
- HDF is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
- "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with HSI/SDK
- Run on Vivado TCL: TE::sw_run_hsi
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
Note: See SDK Projects
- Run on Vivado TCL: TE::sw_run_hsi
SDSoC (only tested on Win OS)
- Generate Platform Project or use prebuilt from download
- ...
Launch
Programming
| HTML |
|---|
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
--> |
| Note |
|---|
Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
QSPI
Not used on this Example.
| HTML |
|---|
<!--
Example:
Connect JTAG and power on PCB
(if not done) Select
correct device and Xilinx install path on "design_basic_settings.cmd"
and create Vivado project with "vivado_create_project_guimode.cmd" or
open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)
--> |
SD
- Copy image.ub and Boot.bin on SD-Card.
- For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section 46039049
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: See TRM of the Carrier, which is used. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
System Design - Vivado
| HTML |
|---|
<!--
Description of Block Design, Constrains...
BD Pictures from Export...
--> |
Block Design
PS Interfaces
Constrains
Basic module constrains
| Code Block | ||||
|---|---|---|---|---|
| ||||
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design] |
Design specific constrain
| Code Block | ||||
|---|---|---|---|---|
| ||||
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]] |
Software Design - SDK/HSI
| HTML |
|---|
<!--
optional chapter
separate sections for different apps
--> |
For SDK project creation, follow instructions from:
Application
FSBL
Xilinx default FSBL
U-Boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
| HTML |
|---|
<!--
optional chapter
Add "No changes." or "Activate: -->List"
--> |
For PetaLinux installation and project creation, follow instructions from:
Config
No changes.
U-Boot
No changes.
Device Tree
| Code Block | ||
|---|---|---|
| ||
/include/ "system-conf.dtsi"
/ {
};
|
Kernel
No changes.
Rootfs
No changes.
Applications
startup
Script App to load init.sh from SD Card if available.
See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files
Additional Software
| HTML |
|---|
<!--
Add Description for other Software, for example SI CLK Builder ...
--> |
No additional software is needed.
SDSoC Design
| HTML |
|---|
<!--
optional chapter for SDSoC only
-remove sections, if not supported
--> |
Description currently not available.
SDSoC Platform
SDSoC Demo Examples
SDSoC platform includes 21 demo projects demonstrating optimization techniques for Standalone and Linux targets with HW acceleration or in SW for fast compilation and debug. These projects have been downloaded and installed into the SDSoC platform from https://github.com/Xilinx/SDSoC_Examples
- array_partition
- burst_rw
- custom_data_type
- data_access_random
- dependence_inter
- direct_connect
- dma_sg
- dma_simple
- full_array_2d
- hello_vadd
- lmem_2rw
- loop_fusion
- loop_perfect
- loop_pipeline
- loop_reorder
- row_array_2d
- shift_register
- systolic_array
- sys_port
- wide_memory_rw
- window_array_2d
There are 3 larger Linux demo projects demonstrating video processing with data I/O from file to file. Source code of these projects have been installed into this platform from the Xilinx SDSoC 2016.4 release:
- file_io_manr_sobel
- file_io_optical
- file_io_sbm
These larger Linux demo projects demonstrate video processing with data I/O from file to file. Source code of these projects have been installed into this platform from demos present in the Xilinx SDSoC 2016.4 release.
Compilation steps in the SDSoC 2017.1 is identical to above described examples. File I/O demos support only the Linux target.
These three files use as an input larger video files. These files have to be present on the SD card as an input. Algorithms write output file to the SD card. These files can be visualized by YUV Player Deluxe and other players. To reduce size of the project, the video data files are not included.
Video input files can be found in the Xilinx SDSoC 2016.4 distribution:
- <xilinx install path>\SDx\2016.4\samples\file_io_manr_sobel\input.yuv
- <xilinx install path>\SDx\2016.4\samples\file_io_optical\route85_1920x1080.yuv
- <xilinx install path>\SDx\2016.4\samples\file_io_sbm\desk_1280x720.yuv
Array partition
This example shows how to use array partitioning to improve performance of a hardware function.
Key Concepts:
- Hardware Function Optimization
- Array Partitioning
Keywords:
- #pragma HLS ARRAY_PARTITION
- complete
Burst rw
This is a simple vector increment example which demonstrates usage of AXI4-master interface for burst read and write.
Key Concepts:
- Burst Access
Custom data type
This is a simple example of RGB to HSV conversion to demonstrate Custom Data Type usage in hardware accelerator. Xilinx HLS compiler supports custom data type to operate within the hardware function and also it acts as a memory interface between PL to DDR.
Key Concepts:
- Custom Data Type
Keywords:
- struct
- packed
- aligned
Data access random
This is a simple example of matrix multiplication (Row x Col) to demonstrate random data access pattern.
Key Concepts:
- Data Access Random
Keywords:
- #pragma HLS PIPELINE
- #pragma SDS access_pattern(a:RANDOM, b:RANDOM)
- #pragma SDS data copy
Dependence inter
This is a simple example to demonstrate inter dependence attribute using vertical convolution example. Using inter dependence attribute user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance.
Key Concepts:
- Inter Dependence
Keywords:
- DEPENDENCE
- inter
Direct connect
This is a simple example of matrix multiplication with matrix addition (Out = (A x B) + C) to demonstrate direct connection which helps to achieve increasing in system parallelism and concurrency.
Key Concepts:
- Direct Connection
- Multiple Accelerators
Keywords:
- #pragma SDS data access_pattern(in1:SEQUENTIAL, in2:SEQUENTIAL, out:SEQUENTIAL)
Dma sg
This example demonstrates how to use Scatter-Gather DMAs for data transfer to/from hardware accelerator.
Key Concepts:
- Scatter Gather DMA
Keywords:
- #pragma SDS access_parttern(a:SEQUENTIAL)
- #pragma SDS data_mover(a:AXIDMA_SG)
- #pragma SDS data copy
Dma simple
This example demonstrates how to insert Simple DMAs for data transfer between User program and hardware accelerator.
Key Concepts:
- Simple DMA
Keywords:
- #pragma SDS access_parttern(a:SEQUENTIAL)
- #pragma SDS data_mover(a:AXIDMA_SIMPLE)
- #pragma SDS data copy
Full array 2d
This is a simple example of accessing full data from 2D array.
Key Concepts:
- 2D data array access
Hello vadd
----------
This is a basic hello world kind of example which demonstrates how to achieve vector addition using hardware function.
Key Concepts:
- - Loop Pipelining
Keywords:
- - #pragma HLS PIPELINE
Lmem 2rw
This is a simple example of vector addition to demonstrate how to utilize both ports of Local Memory.
Key Concepts:
- Hardware Function Optimization
- 2port BRAM Utilization
- Two read/write Local Memory
Keywords:
- #pragma HLS UNROLL FACTOR=2
Loop fusion
This example will demonstrate how to fuse two loops into one to improve the performance of a C/C++ hardware function.
Key Concepts:
- Hardware Function Optimization
- Loop Fusion
- Loop Pipelining
Keywords:
- #pragma HLS PIPELINE
Loop perfect
This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop.
Key Concepts:
- Loop perfect
Keywords:
- #pragma HLS PIPELINE
- #pragma HLS ARRAY_PARTITION
Loop pipeline
This example demonstrates how loop pipelining can be used to improve the performance of a hardware function.
Key Concepts:
- Loop Pipelining
Keywords:
- #pragma HLS PIPELINE
Loop reorder
This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering.
Key Concepts:
- Hardware Function Optimization
- Loop Reorder to Improve II
Keywords:
- #pragma HLS PIPELINE
- #pragma HLS ARRAY_PARTITION
Row array 2d
This is a simple example of accessing each row of data from 2D array.
Key Concepts:
- Row of 2D data array access
Keywords:
- hls::stream
Shift register
This example demonstrates how to shift values in each clock cycle.
Key Concepts:
- Hardware Function Optimization
- Shift Register
- FIR
Keywords:
- #pragma HLS ARRAY_PARTITION
Systolic array
This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA.
Key Concepts:
- Systolic Array
Keywords:
- #pragma HLS PIPELINE
- #pragma HLS ARRAY_PARTITION
Sys port
This is a simple example which demonstrates sys_port usage.
Key Concepts:
- sys_port
- memory interface
- memory non-caching
Keywords:
- #pragma SDS data sys_port
- #pragms HLS PIPELINE
- sds_alloc_non_cacheable
Wide memory rw
This is a simple example of vector addition to demonstrate Wide Memory Access using structure data type of 128bit wide. Based on input argument type, sds++ compiler will figure out the memory interface datawidth of hardware accelerator.
Key Concepts:
- wide memory access
- burst read and write
- custom datatype
Keywords:
- struct
Window array 2d
This is a simple example of accessing window of data from 2D array.
Key Concepts:
- Window of 2D data array access
Keywords:
- #pragma HLS DATAFLOW
- #pragma HLS PIPELINE
- #pragma HLS stream
File IO Video Processing
Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing includes Motion Adaptive Noise Reduction (MANR) followed by a Sobel filter for edge detection. You can run it by supplying a 1080p YUV422 file as input with limiting number of frames to a maximum of 20 frames.
Key Concepts:
- Video processing from file to file
- Direct connection of HW accelerated blocks
Select the "File IO Video Processing" template an compile for Linux target as project te22. Copy result to root of SD card. Copy also the input file input.yuv (82 944 000 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by comman ./te22.elf ./input.yuv 20 3 ./output.yuv
The output.yuv file contains 20 frames of 1080p vido in YUV422 format with computed edges. Copy output.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).
File IO Dense Optical Flow
Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs LK Dense Optical Flow over two Full HD frames video file. You can run it by supplying a 1080p YUV422 file route85_1920x1080.yuv as input.
Key Concept:s
- Video processing from file to file
- Direct connection of HW accelerated blocks
- Top down methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.
Select the "File IO Dense Optical Flow" template an compile for Linux target as project te23. Copy result to root of SD card. Copy also the input file route85_1920x1080.yuv (8 294 400 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te23.elf
The OptFlow_1920x1080.yuv file is generated and stored on the SD card. It contains one 1080p frame in YUV422 format with computed dense optical flow vectors. Copy OptFlow_1920x1080.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).
File IO Stereo Block Matching
Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs Stereo Block Matching to calculate depth in a single sample stereo video file desk_1280x720.yuv in YUV422 format as input and single frame Disparity_640x720.yuv in YUV422 format as output, indicating the depth of objects.
Key Concepts:
- Video processing from file to file
- Bottom Up methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.
Select the "File IO Stereo Block Matching" template an compile for Linux target as project te24. Copy result to root of SD card. Copy also the input file desk_1280x720.yuv (1 843 200 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te24.elf
The Disparity_640x720.yuv file is generated and stored on the SD card. It contains one 640x720 frame in YUV422 format indicating the depth of objects. Copy Disparity_640x720.yuv file to PC and visualise it in yuvplayer (size 640x720 colour YUV422) The input file desk_1280x720.yuv can be visualised by yuvplayer (size 1280x720 colour YUV422). It contains side by side two colour frames from a stereo camera.
Appx. A: Change History and Legal Notices
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
| HTML |
|---|
<!--
Generate new entry:
1:add new row below first
2:Copy Page Information Macro(date+user) Preview, Page Information Macro Preview
3.Update Metadate =Page Information Macro Preview+1
--> |
...
...
Overview
Content Tools