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The Xilinx FPGA itself on the Trenz Electronic USB FX2 modules is blank when powered off. To define an FPGA functionality, a logic architecture Logic Architecture Layer (also called FPGA image or FPGA bitstream) should be defined and loaded into the device at power-on.

The reference design architecture was built using Xilinx Embedded Development Kit (EDK). Basically, it is an embedded system on a chip with a Xilinx MicroBlaze 32-bit soft microprocessor. The MicroBlaze i(MB) nitializes and sets up the system.
Standard EDK cores are used to implement a serial interface (XPS_UARTLITE), an SPI FLASH interface (XPS_SPI), a timer / counter block (XPS_TIMER) and an interrupt controller (XPS_INTC).
Besides standard IP cores, the reference architecture contains three custom IP cores:

1. XPS_I2C_SLAVE: forwards commands coming from the USB bus towards the MicroBlaze.
2. XPS_NPI_DMA: custom DMA between DDR SDRAM and other multiple sources;
3. XPS_FX2: used for high speed bidirectional communication between the FPGA and a host PC;

XPS_I2C_SLAVE is a logic block for low speed bidirectional communication between the FPGA and a host PC. It is usually used for command, settings and status communication. It contains 6 × 32-bit memory mapped registers:

• 3 for host => FPGA communication (FX22MB registers)
• 3 for FPGA => host communication (MB2FX2 registers)

...

Logic Architecture Layer is defined in a .mcs or .bit file (.bin file is also possible). The Logic Architecture Layer is defined (and .bit/.bin/.mcs are created) using the Xilinx software applications:

• XPS, if MicroBlaze is not used

• EDK (or both), if MicroBlaze is used.

The Logic Architecture Layer could be loaded from SPI Flash (it happens automatically at power on or on general reset) or from JTAG and/or USB connections. See here for a general introduction.