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  • Formatting was changed.


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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"


DateVersionChangesAuthor
2023-12-143.1.17
  • updated according to Vivado 2023.2
ma
2023-06-133.1.16
  • Design flow:
    • added alternative programming files in Petalinux
  • added chapter FSBL Patch in Software Design - Petalinux
ma
2023-06-013.1.15
  • removed u-boot.dtb from Design flow
ma
2023-06-013.1.14
  • expandable lists for revision history and supported hardware
wh
2023-05-253.1.13
  • updated according to Vivado 2022.2
ma
2023-02-083.1.12
  • removed content of
    • Special FSBL for QSPI programming
ma
2022-08-243.1.11
  • Modification from link "available short link"
ma
2022-01-253.1.10
  • removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
  • corrected Boot Source File in Boot Script-File
ma
2022-01-143.1.9
  • extended notes for microblaze boot process with linux
  • add u.boot.dtb to petalinux notes
  • add dtb to prebuilt content
  • replace 20.2 with 21.2
jh
2021-06-283.1.8
  • added boot process for Microblaze
  • minor typos, formatting
ma
2021-06-013.1.7
  • carrier reference note
jh
2021-05-043.1.6
  • removed zynq_ from zynq_fsbl
ma
2021-04-283.1.5
  • added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
  • minor typos, formatting
ma
2021-04-273.1.4
  • Version History
    • changed from list to table
  • Design flow
    • removed step 5 from Design flow
    • changed link from TE Board Part Files to Vivado Board Part Flow
    • changed cmd shell from picture to codeblock
    • added hidden template for "Copy PetaLinux build image files", depending from hardware
    • added hidden template for "Power on PCB", depending from hardware
  • Usage update of boot process
  • Requirements - Hardware
    • added "*used as reference" for hardware requirements
  • all
    • placed a horizontal separation line under each chapter heading
    • changed title-alignment for tables from left to center
  • all tables
    • added "<project folder>\board_files" in Vivado design sources
ma

3.1.3
  • Design Flow
    • formatting
  • Launch
    • formatting
ma

3.1.2
  • minor typing corrections
  • replaced SDK by Vitis
  • changed from / to \ for windows paths
  • replaced <design name> by <project folder>
  • added "" for path names
  • added boot.src description
  • added USB for programming
ma

3.1.1
  • swapped order from prebuilt files
  • minor typing corrections
  • removed Win OS path length from Design flow, added as caution in Design flow
ma

3.1
  • Fix problem with pdf export and side scroll bar
  • update 19.2 to 20.2
  • add prebuilt content option


3.0
  • add fix table of content
  • add table size as macro
  • removed page initial creator


Custom_table_size_100
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Important General Note:

  • Export PDF to download, if vivado revision is changed!

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
      • Figure template (note: inner scroll ignore/only only with drawIO object):

        Scroll Title
        anchorFigure_xyz
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, use


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables
        • Set column width manually (can be used for small tables to fit over whole page) or leave empty (automatically)

      • Scroll Title
        anchorTable_xyz
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
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        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



  • ...

Overview

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scroll-eclipsehelptrue
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Notes :

Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.

Refer to http://trenz.org/te0808-info for the current online version of this manual and other available documentation.

Key Features

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Notes :

  • Add basic key futures, which can be tested with the design


Excerpt
  • Vitis/Vivado 2023.2
  • QSPI
  • Custom Carrier (minimum PS Design with available module components only)
  • Modified FSBL (some additional outputs only)

Revision History

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Notes :

  • add every update file on the download
  • add design changes on description
Expand
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DateVivadoProject BuiltAuthorsDescription
2024-05-292023.2TE0808-test_board-vivado_2023.2-build_4_20240528102532.zip
TE0808-test_board_noprebuilt-vivado_2023.2-build_4_20240528102532.zip
Manuela Strücker
  • new assembly variants
2024-03-132023.2TE0808-test_board-vivado_2023.2-build_4_20240313130413.zip
TE0808-test_board_noprebuilt-vivado_2023.2-build_4_20240313130413.zip
Manuela Strücker
  • 2023.2 release
  • new assembly variants
2023-06-012022.2TE0808-test_board-vivado_2022.2-build_1_20230601101432.zip
TE0808-test_board_noprebuilt-vivado_2022.2-build_1_20230601101432.zip
Manuela Strücker
  • 2022.2 release
  • new assembly variants
2023-04-132021.2.1TE0808-test_board-vivado_2021.2-build_20_20230413090245.zip
TE0808-test_board_noprebuilt-vivado_2021.2-build_20_20230413090245.zip
Manuela Strücker
  • new assembly variants
2022-09-292021.2.1TE0808-test_board-vivado_2021.2-build_17_20220928203325.zip
TE0808-test_board_noprebuilt-vivado_2021.2-build_17_20220928203325.zip
Manuela Strücker
  • script update
  • new assembly variants
2022-09-122021.2.1TE0808-test_board-vivado_2021.2-build_15_20220912090608.zip
TE0808-test_board_noprebuilt-vivado_2021.2-build_15_20220912090608.zip
Manuela Strücker
  • update board part files compatible to Vivado 2021.2.1
2022-03-212021.2TE0808-test_board-vivado_2021.2-build_11_20220321063547.zip
TE0808-test_board_noprebuilt-vivado_2021.2-build_11_20220321063547.zip
John Hartfiel
  • replace Starterkit FSBL with default one
2022-03-162021.2TE0808-test_board-vivado_2021.2-build_11_20220316091917.zip
TE0808-test_board_noprebuilt-vivado_2021.2-build_11_20220316091917.zip
Manuela Strücker
  • 2021.2 release
  • update board files
2021-05-122020.2TE0808-test_board-vivado_2020.2-build_5_20210512133121.zip
TE0808-test_board_noprebuilt-vivado_2020.2-build_5_20210512133137.zip
John Hartfiel
  • update board files
2021-02-052020.2TE0808-test_board-vivado_2020.2-build_0_20210204141911.zip
TE0808-test_board_noprebuilt-vivado_2020.2-build_1_20210204142855.zip
John Hartfiel
  • 2020.2 update
2020-09-292019.2TE0808-test_board_noprebuilt-vivado_2019.2-build_15_20200929070740.zip
TE0808-test_board-vivado_2019.2-build_15_20200929070725
John Hartfiel
  • bugfix 8GB board parts
2020-09-222019.2TE0808-test_board_noprebuilt-vivado_2019.2-build_14_20200922073159.zip
TE0808-test_board-vivado_2019.2-build_14_20200922073144.zip
John Hartfiel
  • new assembly variants
2020-03-252019.2TE0808-test_board_noprebuilt-vivado_2019.2-build_8_20200325083246.zip
TE0808-test_board-vivado_2019.2-build_8_20200325083204.zip
John Hartfiel
  • script update
2020-01-222019.2TE0808-test_board_noprebuilt-vivado_2019.2-build_3_20200122142231.zip
TE0808-test_board-vivado_2019.2-build_3_20200122142208.zip
John Hartfiel
  • 2019.2 update
  • Vitis support
2019-08-092018.3TE0808-test_board_noprebuilt-vivado_2018.3-build_07_20190809131546.zip
TE0808-test_board-vivado_2018.3-build_07_20190809131522.zip
John Hartfiel
  • new assembly variants
2019-05-062018.3TE0808-test_board_noprebuilt-vivado_2018.3-build_05_20190507124141.zip
TE0808-test_board-vivado_2018.3-build_05_20190507124130.zip
John Hartfiel
  • custom FSBL
2018-07-112018.2TE0808-test_board_noprebuilt-vivado_2018.2-build_02_20180711143743.zip
TE0808-test_board-vivado_2018.2-build_02_20180711143702.zip
John Hartfiel
  • additional notes for FSBL generated with Win SDK
  • changed *.bif
2018-03-292017.4TE0808-test_board-vivado_2017.4-build_07_20180329151341.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_07_20180329151355.zip
John Hartfiel
  • new assembly variant
2018-01-162017.4TE0808-test_board-vivado_2017.4-build_04_20180116144644.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_04_20180116144657.zip
John Hartfiel
  • Update Board Part for TEBF0808
    • no changes for test board design and minimal board parts
2018-01-152017.4TE0808-test_board-vivado_2017.4-build_03_20180115084954.zip
TE0808-test_board_noprebuilt-vivado_2017.4-build_03_20180115085020.zip
John Hartfiel
  • rework Board Part Files
2017-12-202017.2

TE0808-test_board-vivado_2017.2-build_07_20171220192501.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_07_20171220192448.zip

John Hartfiel
  • Update Board Part Files
2017-11-222017.2TE0808-test_board-vivado_2017.2-build_05_20171122080211.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171122080228.zip
John Hartfiel
  • Update Board Part CSV File
  • Regenerate design
2017-11-162017.2

TE0808-test_board-vivado_2017.2-build_05_20171116151545.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171116151600.zip

John Hartfiel
  • Update Board Part CSV File with new Flash assembly variants
2017-11-132017.2TE0808-test_board-vivado_2017.2-build_05_20171113140954.zip
TE0808-test_board_noprebuilt-vivado_2017.2-build_05_20171113141908.zip
John Hartfiel
  • initial release



Release Notes and Know Issues

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Notes :
  • add known Design issues and general notes for the current revision
  • do not delete known issue, add fixed version time stamp if issue fixed
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IssuesDescriptionWorkaroundTo be fixed version
QSPI FlashFlash programming is not supported with boot mode QSPI or SD.
If flash programming fails, configure device for JTAG boot mode and try again or use older Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
--


Requirements

Software

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Notes :

  • list of software which was used to generate the design
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SoftwareVersionNote
Vitis2023.2needed, Vivado is included into Vitis installation



Hardware

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Notes :

  • list of hardware which was used to generate the design
  • mark the module and carrier board, which was used tested with an *
Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on "<project folder>\board_files\*_board_files.csv"

Design supports following modules:

Expand
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Module ModelBoard Part Short NamePCB Revision SupportDDRQSPI FlashEMMCOthersNotes
TE0808-ES1          es1_2gb      REV03|REV02 2GB      64MB       NA         NA               Not longer supported by vivado       
TE0808-ES2          es2_2gb      REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado          
TE0808-2ES2         2es2_2gb     REV04|REV03 2GB      64MB       NA         NA               Not longer supported by vivado        
TE0808-04-06EG-1E36eg_1e_4gbREV044GB128MBNA1 mm connectorsNA
TE0808-04-06EG-1EE6eg_1e_4gbREV044GB128MBNANANA
TE0808-04-09EG-1EA9eg_1e_2gbREV042GB64MBNANANA
TE0808-04-09EG-1EB9eg_1e_4gbREV044GB64MBNANANA
TE0808-04-09EG-1ED9eg_1e_4gbREV044GB64MBNA1 mm connectorsNA
TE0808-04-09EG-1EE9eg_1e_4gbREV044GB128MBNANANA
TE0808-04-09EG-1EL9eg_1e_4gbREV044GB128MBNA1 mm connectorsNA
TE0808-04-09EG-2IB9eg_2i_4gbREV044GB64MBNANANA
TE0808-04-09EG-2IE9eg_2i_4gbREV044GB128MBNANANA
TE0808-04-6BE21-A6eg_1e_4gbREV044GB128MBNANANA
TE0808-04-6BE21-L6eg_1e_4gbREV044GB128MBNA1 mm connectorsNA
TE0808-04-6BI21-A6eg_1i_4gbREV044GB128MBNANANA
TE0808-04-6BI21-X6eg_1i_4gbREV044GB128MBNANAU41 replaced with schottky diodes
TE0808-04-6GI21-L6eg_2i_4gbREV044GB128MBNA1 mm connectorsNA
TE0808-04-9BE21-A9eg_1e_4gbREV044GB128MBNANANA
TE0808-04-9BE21-L9eg_1e_4gbREV044GB128MBNA1 mm connectorsNA
TE0808-04-9GI21-A9eg_2i_4gbREV044GB128MBNANANA
TE0808-04-15EG-1EB15eg_1e_4gbREV044GB64MBNANANA
TE0808-04-15EG-1EE15eg_1e_4gbREV044GB128MBNANANA
TE0808-04-BBE21-A15eg_1e_4gbREV044GB128MBNANANA
TE0808-05-6BE21-A6eg_1e_4gbREV054GB128MBNANANA
TE0808-05-6BE21-F6eg_1e_4gbREV054GB128MBNANANA
TE0808-05-6BE21-AK6eg_1e_4gbREV054GB128MBNANANA
TE0808-05-6BE21-L6eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-6BI21-D6eg_1i_4gbREV054GB128MBNA1 mm connectorsSoC without encryption
TE0808-05-6BI21-X6eg_1i_4gbREV054GB128MBNANAU41 replaced with schottky diodes
TE0808-05-6BI41-X6eg_1i_8gbREV058GB128MBNANASingle Die DDR; U41 replaced with schottky diodes
TE0808-05-9BE21-A9eg_1e_4gbREV054GB128MBNANANA
TE0808-05-9BE21-AK9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-9BE21-AZ9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-9BE21-E9eg_1e_4gbREV054GB128MBNANANA
TE0808-05-9BE21-F9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-9BE21-KZ9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-9BE21-L9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-9BE21-LK9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-9BE21-LZ9eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-9BE81-A9eg_1e_4gbREV054GB128MBNANANA
TE0808-05-9BI41-X9eg_1i_8gbREV058GB128MBNANASingle Die DDR; U41 replaced with schottky diodes
TE0808-05-9GI21-A9eg_2i_4gbREV054GB128MBNANANA
TE0808-05-9GI21-AK9eg_2i_4gbREV054GB128MBNANANA
TE0808-05-9GI21-AZ9eg_2i_4gbREV054GB128MBNANANA
TE0808-05-9GI21-C9eg_2i_4gbREV054GB128MBNANASoC without encryption
TE0808-05-9GI21-E9eg_2i_4gbREV054GB128MBNANANA
TE0808-05-9GI21-KZ9eg_2i_4gbREV054GB128MBNACAOCAO
TE0808-05-BBE21-A15eg_1e_4gbREV054GB128MBNANANA
TE0808-05-BBE21-AK15eg_1e_4gbREV054GB128MBNANANA
TE0808-05-BBE21-AZ15eg_1e_4gbREV054GB128MBNANANA
TE0808-05-BBE21-E15eg_1e_4gbREV054GB128MBNANANA
TE0808-05-BBE21-L15eg_1e_4gbREV054GB128MBNA1 mm connectorsNA
TE0808-05-BBE81-A15eg_1e_4gbREV054GB128MBNANANA
TE0808-05-BBE81-E15eg_1e_4gbREV054GB128MBNANANA
TE0808-05-BBE81-EK15eg_1e_4gbREV054GB128MBNANANA
TE0808-05-S0019eg_1e_8gb_DREV058GB128MBNACAOCAO;Single Die DDR
TE0808-05-S00215eg_1e_4gbREV054GB128MBNACAOCAO
TE0808-05-S00315eg_1e_4gbREV054GB128MBNACAOCAO
TE0808-05-S0049eg_2i_4gbREV054GB128MBNACAOCAO
TE0808-05-S0059eg_2i_4gbREV054GB128MBNACAOCAO
TE0808-05-S0069eg_2i_4gbREV054GB128MBNACAOCAO
TE0808-05-S0079eg_1e_4gbREV054GB128MBNANACAO
TE0808-05-S0149eg_1e_4gbREV054GB128MBNANACAO
TE0808-05-S0169eg_1e_4gbREV054GB128MBNACAOCAO
TE0808-05-S0189eg_2e_4gbREV054GB128MBNACAOCAO
TE0808-05-S0199eg_2e_4gbREV054GB128MBNACAOCAO
TE0808-05-S0209eg_2i_4gbREV054GB128MBNACAOCAO
TE0808-05-S0219eg_2i_4gbREV054GB128MBNACAOCAO
TE0808-05-S0226cg_1e_4gbREV054GB128MBNACAOCAO
TE0808-05-S0256eg_1e_4gb_DREV054GB128MBNACAOCAO
TE0808-05-S0269eg_2i_4gbREV054GB128MBNACAO:Si5345 not assembledCAO: without PLL
TE0808-05-S0279eg_2i_4gbREV054GB128MBNACAOCAO
TE0808-05-S0299eg_2i_4gbREV054GB128MBNACAOCAO
TE0808-05-S03315eg_1e_4gbREV054GB128MBNANACAO
TE0808-05-S03515eg_1e_4gbREV054GB128MBNACAOCAO
TE0808-05-S03615eg_1e_4gbREV054GB128MBNACAOCAO
TE0808-05-S0389eg_1e_4gbREV054GB128MBNACAOCAO
TE0808-05-S0396eg_1e_4gbREV054GB128MBNACAOCAO: without PLL
TE0808-05-S0416eg_1e_4gb_DREV054GB128MBNACAOCAO

*used as reference


Note: Design contains also Board Part Files for TE0808+TEBF0808 configuration, this board part files are not used for this reference design.

Design supports following carriers:

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Carrier ModelNotes
Custom PCBuse simple Board Part files, if MIO connected is different to TEBF0808
TEBF0808*Used as reference carrier.
TEBT0808-01Change UART0 to UART1 (MIO68...69) and regenerate design

*used as reference


Additional HW Requirements:

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Additional HardwareNotes
------

*used as reference

Content

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Notes :

  • content of the zip file
For general structure and usage of the reference design, see Project Delivery - AMD devices

Design Sources

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TypeLocationNotes
Vivado<project folder>\block_design
<project folder>\constraints
<project folder>\ip_lib
<project folder>\board_files
Vivado Project will be generated by TE Scripts
Vitis<project folder>\sw_libAdditional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation



Additional Sources

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TypeLocationNotes
---------


Prebuilt

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Notes :

  • prebuilt files
  • Template Table:

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      File

      File-Extension

      Description

      BIF-File*.bifFile with description to generate Bin-File
      BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
      BIT-File*.bitFPGA (PL Part) Configuration File
      Boot Script-File*.scr

      Distro Boot Script file

      DebugProbes-File*.ltxDefinition File for Vivado/Vivado Labtools Debugging Interface

      Debian SD-Image

      *.img

      Debian Image for SD-Card

      Diverse Reports---Report files in different formats
      Device Tree*.dtsDevice tree (2 possible, one for u-boot and one for linux)
      Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
      LabTools Project-File*.lprVivado Labtools Project File

      MCS-File

      *.mcs

      Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

      MMI-File

      *.mmi

      File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

      OS-Image*.ubImage with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)
      Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems

      SREC-File

      *.srec

      Converted Software Application for MicroBlaze Processor Systems



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File

File-Extension

Description

BIF-File*.bifFile with description to generate Bin-File
BIN-File*.binFlash Configuration File with Boot-Image (Zynq-FPGAs)
BIT-File*.bitFPGA (PL Part) Configuration File
Diverse Reports---Report files in different formats
Hardware-Platform-Description-File*.xsaExported Vivado hardware description file for Vitis and PetaLinux
LabTools Project-File*.lprVivado Labtools Project File
Software-Application-File*.elfSoftware Application for Zynq or MicroBlaze Processor Systems


Download

Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Notes :
  • Basic Design Steps

  • Add/ Remove project specific description


Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

Note

Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>")

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:

    Code Block
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    themeMidnight
    title_create_win_setup.cmd/_create_linux_setup.sh
    ------------------------Set design paths----------------------------
    -- Run Design with: _create_win_setup
    -- Use Design Path: <absolute project path>
    --------------------------------------------------------------------
    -------------------------TE Reference Design---------------------------
    --------------------------------------------------------------------
    -- (0)  Module selection guide, project creation...prebuilt export...
    -- (1)  Create minimum setup of CMD-Files and exit Batch
    -- (2)  Create maximum setup of CMD-Files and exit Batch
    -- (3)  (internal only) Dev
    -- (4)  (internal only) Prod
    -- (c)  Go to CMD-File Generation (Manual setup)
    -- (d)  Go to Documentation (Web Documentation)
    -- (g)  Install Board Files from Xilinx Board Store (beta)
    -- (a)  Start design with unsupported Vivado Version (beta)
    -- (x)  Exit Batch (nothing is done!)
    ----
    Select (ex.:'0' for module selection guide):


  2. Press 0 and enter to start "Module Selection Guide"
  3. Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
    • optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"

      Note

      Note: Select correct one, see also Vivado Board Part Flow

      Important: Use Board Part Files, which did not end with *_tebf0808


  4. Create hardware description file (.xsa file) and export to prebuilt folder

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>")
    TE::hw_build_design -export_prebuilt


    Info

    Using Vivado GUI is the same, except file export to prebuilt folder.


  5. Generate Programming Files with Vitis

    Code Block
    languagepy
    themeMidnight
    titlerun on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv")
    TE::sw_run_vitis -all
    TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL)


    Note

    TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis



Launch

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Note:

  • Programming and Startup procedure

Programming

Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch.

Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging

Get prebuilt boot binaries

  1. Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
  2. Press 0 and enter to start "Module Selection Guide"
    1. Select assembly version
    2. Validate selection
    3. Select create and open delivery binary folder

      Info

      Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated


QSPI-Boot mode

  1. Connect JTAG and power on carrier with module
  2. Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"

    Code Block
    languagebash
    themeMidnight
    titlerun on Vivado TCL (Script programs BOOT.bin on QSPI flash)
    TE::pr_program_flash -swapp hello_te0808


SD-Boot mode

This does not work, because SD controller is not selected on PS.

JTAG

Load configuration and Application with Vitis Debugger into device

Usage

QSPI Boot:

  1. Prepare HW like described on section Programming
  2. Connect UART USB (most cases same as JTAG)
  3. Select QSPI as Boot Mode

    Info

    Note: See TRM of the Carrier, which is used.


  4. Power On PCB

    Expand
    titleboot process

    1. ZynqMP Boot ROM FSBL from QSPI into OCM,

    2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR


System Design - Vivado

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Note:

  • Description of Block Design, Constrains... BD Pictures from Export...

Block Design

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PS Interfaces

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  • optional for Zynq / ZynqMP only

  • add basic PS configuration
Activated interfaces:
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TypeNote
DDR
QSPIMIO
UART0MIO, please select other one, if you have connected UART to second controller or other MIO
SWDT0..1
TTC0..3


Constrains

Basic module constrains

Code Block
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title_i_bitgen.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design]

Design specific constrain

Not needed.

Software Design - Vitis

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Note:
  • optional chapter separate

  • sections for different apps

For Vitis project creation, follow instructions from:

Vitis

Application

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----------------------------------------------------------

FPGA Example

----------------------------------------------------------

scu

MCS Firmware to configure SI5338 and Reset System.

srec_spi_bootloader

TE modified 2023.2 SREC

Bootloader to load app or second bootloader from flash into DDR

Descriptions:

  • Modified Files: blconfig.h, bootloader.c
  • Changes:
    • Add some console outputs and changed bootloader read address.
    • Add bugfix for 2018.2 qspi flash

xilisf_v5_11

TE modified 2023.2 xilisf_v5_11

  • Changed default Flash type to 5.

----------------------------------------------------------

Zynq Example:

----------------------------------------------------------

fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_fsbl_hooks.h/.c (for hooks and board)

  • General Changes: 
    • Display FSBL Banner and Device ID

Module Specific:

  • Add Files: all TE Files start with te_*
    • READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
    • CPLD access
    • Read CPLD Firmware and SoC Type
    • Configure Marvell PHY


----------------------------------------------------------

ZynqMP Example:

----------------------------------------------------------

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

Module Specific:

  • Add Files: all TE Files start with te_*
    • Si5338 Configuration
    • ETH+OTG Reset over MIO

zynqmp_pmufw

Xilinx default PMU firmware.

----------------------------------------------------------

General Example:

----------------------------------------------------------

hello_te0820

Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.

u-boot

U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.

Template location: "<project folder>\sw_lib\sw_apps\"

zynqmp_fsbl

TE modified 2023.2 FSBL

General:

  • Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
  • Add Files: te_xfsbl_hooks.h/.c (for hooks and board)
  • General Changes: 
    • Display FSBL Banner and Device Name

hello_te0808

Hello TE0808 is a Xilinx Hello World example as endless loop instead of one console output.

Additional Software

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Note:
  • Add description for other Software, for example SI CLK Builder ...
  • SI5338 and SI5345 also Link to:
No additional software is needed.

Appx. A: Change History and Legal Notices

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Document Change History

To get content of older revision go to "Change History" of this page and select older document revision number.

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    • Metadata is only used of compatibility of older exports


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DateDocument Revision

Authors

Description

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
typeFlat

  • new assembly variants
2024-03-14v.46Manuela Strücker
  • 2023.2 release
  • new assembly variants
2023-06-14v.45Manuela Strücker
  • 2022.2 release
  • new assembly variants
2023-04-13v.43Manuela Strücker
  • new assembly variants
2022-09-29v.41Manuela Strücker
  • script update
  • new assembly variants
2022-09-12v.40Manuela Strücker
  • update board part files compatible to Vivado 2021.2.1
2022-09-06v.38Manuela Strücker
  • Design Bugfix
2022-03-16v.36Manuela Strücker
  • Release 2021.2
2021-05-25v.35Manuela Strücker
  • Document Style update

2021-05-12

v.34

John Hartfiel

  • update board files
2021-02-05v.33John Hartfiel
  • Release 2020.2
  • Document Style update
2021-02-05v.31John Hartfiel
  • new assembly variants
2020-03-25v.28John Hartfiel
  • script update
2020-01-27v.27John Hartfiel
  • documentation update
2020-01-22v.26John Hartfiel
  • new assembly variants
  • Release 2019.2
2019-08-09v.24John Hartfiel
  • new assembly variants
  • small document style update
2019-05-07v.22John Hartfiel
  • Release 2018.3
2018-07-11v.21John Hartfiel
  • Release 2018.2

2018-03-29

v.20John Hartfiel
  • new assembly variant
2018-02-08v.19John Hartfiel
  • Release 2017.4
2017-12-20v.14John Hartfiel
  • Design Update
  • typo correction on documentation
2017-11-22v.10John Hartfiel
  • Update assembly versions with new Flash size
  • Update HW Table Name
  • Update Design
2017-11-14v.6John Hartfiel
  • Release 2017.2
--all

Page info
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typeFlat

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Table of contents

Table of Contents
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Overview

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Key Features

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Excerpt
  • PetaLinux
  • SD
  • ETH
  • USB
  • I2C
  • RTC
  • FMeter

Revision History

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Release Notes and Know Issues

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Requirements

Software

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...

Hardware

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Hardware Support
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Basic description of TE Board Part Files is available on TE Board Part Files.

Complete List is available on <design name>/board_files/*_board_files.csv

Design supports following modules:

...

Design supports following carriers:

...

Additional HW Requirements:

...

Content

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For general structure and of the reference design, see Project Delivery

Design Sources

...

Additional Sources

...

Prebuilt

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<tr> <td>BIF-File                             </td> <td>*.bif         </td>  <td>File with description to generate Bin-File                                               </td> </tr>
<tr> <td>BIN-File                             </td> <td>*.bin         </td>  <td>Flash Configuration File with Boot-Image (Zynq-FPGAs)                                    </td> </tr>
<tr> <td>BIT-File                             </td> <td>*.bit         </td>  <td>FPGA Configuration File                                                                  </td> </tr>
<tr> <td>DebugProbes-File                     </td> <td>*.ltx         </td>  <td>Definition File for Vivado/Vivado Labtools Debugging Interface                           </td> </tr>
<tr> <td>Debian SD-Image                      </td> <td>*.img         </td>  <td>Debian Image for SD-Card                                                                </td> </tr>
<tr> <td>Diverse Reports                      </td> <td>  ---         </td>  <td>Report files in different formats                                                        </td> </tr>
<tr> <td>Hardware-Platform-Specification-Files</td> <td>*.hdf         </td>  <td>Exported Vivado Hardware Specification for SDK/HSI                                       </td> </tr>
<tr> <td>LabTools Project-File                </td> <td>*.lpr         </td>  <td>Vivado Labtools Project File                                                             </td> </tr>
<tr> <td>MCS-File                             </td> <td>*.mcs         </td>  <td>Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)                  </td> </tr>
<tr> <td>MMI-File                             </td> <td>*.mmi         </td>  <td>File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) </td> </tr>
<tr> <td>OS-Image                             </td> <td>*.ub          </td>  <td>Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk)             </td> </tr>
<tr> <td>Software-Application-File            </td> <td>*.elf         </td>  <td>Software Application for Zynq or MicroBlaze Processor Systems                            </td> </tr>
<tr> <td>SREC-File                            </td> <td>*.srec        </td>  <td>Converted Software Application for MicroBlaze Processor Systems                          </td> </tr>    
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File-Extension

...

Description

...

Debian SD-Image

...

*.img

...

Debian Image for SD-Card

...

MCS-File

...

*.mcs

...

Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)

...

MMI-File

...

*.mmi

...

File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)

...

SREC-File

...

*.srec

...

Converted Software Application for MicroBlaze Processor Systems

Download

Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.

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Reference Design is available on:

Design Flow

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Basic Design Steps
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Note

Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch.

Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.

See also:

The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.

TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI.  For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality

 

  1. _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
    Image Removed
  2. Press 0 and enter for minimum setup
  3. (optional Win OS) Generate Virtual Drive or use short directory  for the reference design (for example x:\<design name>)
  4. Create Project
    1. Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
      Note: Select correct one, see TE Board Part Files
  5. Create HDF and export to prebuilt folder
    1. Run on Vivado TCL: TE::hw_build_design -export_prebuilt
      Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
  6. Create Linux (uboot.elf and image.ub) with exported HDF
    1. HDF is exported to "prebuilt\hardware\<short name>"
      Note: HW Export from Vivado GUI create another path as default workspace.
    2. Create Linux images on VM, see PetaLinux KICKstart
      1. Use TE Template from /os/petalinux
        Note: run init_config.sh before you start petalinux config. This will set correct temporary path variable.
  7. Add Linux files (uboot.elf and image.ub) to prebuilt folder
    1. "prebuilt\os\petalinux\default" or "prebuilt\os\petalinux\<short name>"
      Notes: Scripts select "prebuilt\os\petalinux\<short name>", if exist, otherwise "prebuilt\os\petalinux\default"
  8. Generate Programming Files with HSI/SDK
    1. Run on Vivado TCL: TE::sw_run_hsi
      Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
    2. (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_sdk
      Note: See SDK Projects

SDSoC (only tested on Win OS)

  1. Generate Platform Project or use prebuilt from download
  2. ...

Launch

Programming

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Note

Check Module and Carrier TRMs for proper HW configuration before you try any design.

Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging

QSPI

Not used on this Example.

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open with "vivado_open_project_guimode.cmd", if generated.
Type on Vivado Console: TE::pr_program_flash_mcsfile -swapp u-boot
Note: Alternative use SDK or setup Flash on Vivado manually
Reboot (if not done automatically)

   -->

SD

  1. Copy image.ub and Boot.bin on SD-Card.
    • For correct prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
  2. Set Boot Mode to SD-Boot.
    • Depends on Carrier, see carrier TRM.
  3. Insert SD-Card in SD-Slot.

JTAG

Not used on this Example.

Usage

  1. Prepare HW like described on section 46039049
  2. Connect UART USB (most cases same as JTAG)
  3. Select SD Card as Boot Mode
    Note: See TRM of the Carrier, which is used.
  4. Power On PCB
    Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR, 3. U-boot load Linux from SD into DDR

Linux

  1. Open Serial Console (e.g. putty)
    1. Speed: 115200
    2. COM Port: Win OS, see device manager, Linux OS see  dmesg |grep tty  (UART is *USB1)
  2. Linux Console:
    Note: Wait until Linux boot finished For Linux Login use:
    1. User Name: root
    2. Password: root

 

System Design - Vivado

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Block Design

PS Interfaces

Constrains

Basic module constrains

Code Block
languageruby
title_i_bitgen_common.xdc
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]

set_property BITSTREAM.CONFIG.USR_ACCESS TIMESTAMP [current_design]

Design specific constrain

Code Block
languageruby
title_i_io.xdc
set_property PACKAGE_PIN K2 [get_ports {fclk[0]}]
set_property IOSTANDARD LVCMOS18 [get_ports {fclk[0]}]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets fclk_IBUF[0]]

Software Design - SDK/HSI

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For SDK project creation, follow instructions from:

SDK Projects

Application

FSBL

Xilinx default FSBL

U-Boot

U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.

Software Design -  PetaLinux

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For PetaLinux installation and  project creation, follow instructions from:

Config

No changes.

U-Boot

No changes.

Device Tree

Code Block
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/include/ "system-conf.dtsi"
/ {
};


Kernel

No changes.

Rootfs

No changes.

Applications

startup

Script App to load init.sh from SD Card if available.

See: \os\petalinux\project-spec\meta-user\recipes-apps\startup\files

Additional Software

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No additional software is needed.

SDSoC Design

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Description currently not available.

SDSoC Platform

SDSoC Demo Examples

SDSoC platform includes 21 demo projects demonstrating optimization techniques for Standalone and Linux targets with HW acceleration or in SW for fast compilation and debug. These projects have been downloaded and installed into the SDSoC platform from https://github.com/Xilinx/SDSoC_Examples

  • array_partition
  • burst_rw
  • custom_data_type
  • data_access_random
  • dependence_inter
  • direct_connect
  • dma_sg
  • dma_simple
  • full_array_2d
  • hello_vadd
  • lmem_2rw
  • loop_fusion
  • loop_perfect
  • loop_pipeline
  • loop_reorder
  • row_array_2d
  • shift_register
  • systolic_array
  • sys_port
  • wide_memory_rw
  • window_array_2d

 

There are 3 larger Linux demo projects demonstrating video processing with data I/O from file to file. Source code of these projects have been installed into this platform from the Xilinx SDSoC 2016.4 release:

  • file_io_manr_sobel
  • file_io_optical
  • file_io_sbm

These larger Linux demo projects demonstrate video processing with data I/O from file to file. Source code of these projects have been installed into this platform from demos present in the Xilinx SDSoC 2016.4 release.

Compilation steps in the SDSoC 2017.1 is identical to above described examples. File I/O demos support only the Linux target.

These three files use as an input larger video files. These files have to be present on the SD card as an input. Algorithms write output file to the SD card. These files can be visualized by YUV Player Deluxe and other players. To reduce size of the project, the video data files are not included.

Video input files can be found in the Xilinx SDSoC 2016.4 distribution:

  • <xilinx install path>\SDx\2016.4\samples\file_io_manr_sobel\input.yuv
  • <xilinx install path>\SDx\2016.4\samples\file_io_optical\route85_1920x1080.yuv
  • <xilinx install path>\SDx\2016.4\samples\file_io_sbm\desk_1280x720.yuv

 

Array partition

This example shows how to use array partitioning to improve performance of a hardware function.

Key Concepts:

  •  Hardware Function Optimization
  •  Array Partitioning

Keywords:

  •  #pragma HLS ARRAY_PARTITION
  •  complete

Burst rw

This is a simple vector increment example which demonstrates usage of AXI4-master interface for burst read and write.

Key Concepts:

  •  Burst Access

Custom data type

This is a simple example of RGB to HSV conversion to demonstrate Custom Data Type usage in hardware accelerator. Xilinx HLS compiler supports custom data type to operate within the hardware function and also it acts as a memory interface between PL to DDR.

Key Concepts:

  •  Custom Data Type

Keywords:

  •  struct
  •  packed
  •  aligned

Data access random

This is a simple example of matrix multiplication (Row x Col) to demonstrate random data access pattern.

Key Concepts:

  •  Data Access Random

Keywords:

  •  #pragma HLS PIPELINE
  •  #pragma SDS access_pattern(a:RANDOM, b:RANDOM)
  •  #pragma SDS data copy

Dependence inter

This is a simple example to demonstrate inter dependence attribute using vertical convolution example. Using inter dependence attribute user can provide additional dependency details to compiler which allow compiler to perform unrolling/pipelining to get better performance.

Key Concepts:

  •  Inter Dependence

Keywords:

  •  DEPENDENCE
  •  inter

Direct connect

This is a simple example of matrix multiplication with matrix addition (Out = (A x B) + C) to demonstrate direct connection which helps to achieve increasing in system parallelism and concurrency.

Key Concepts:

  •  Direct Connection
  •  Multiple Accelerators

Keywords:

  •  #pragma SDS data access_pattern(in1:SEQUENTIAL, in2:SEQUENTIAL, out:SEQUENTIAL)

Dma sg

This example demonstrates how to use Scatter-Gather DMAs for data transfer to/from hardware accelerator.

Key Concepts:

  •  Scatter Gather DMA

Keywords:

  •  #pragma SDS access_parttern(a:SEQUENTIAL)
  •  #pragma SDS data_mover(a:AXIDMA_SG)
  •  #pragma SDS data copy

Dma simple

This example demonstrates how to insert Simple DMAs for data transfer between User program and hardware accelerator.

Key Concepts:

  • Simple DMA

Keywords:

  • #pragma SDS access_parttern(a:SEQUENTIAL)
  • #pragma SDS data_mover(a:AXIDMA_SIMPLE)
  • #pragma SDS data copy

Full array 2d

This is a simple example of accessing full data from 2D array.

Key Concepts:

  •  2D data array access

Hello vadd

----------

This is a basic hello world kind of example which demonstrates how to achieve vector addition using hardware function.

Key Concepts:

  •  - Loop Pipelining

Keywords:

  •  - #pragma HLS PIPELINE

Lmem 2rw

This is a simple example of vector addition to demonstrate how to utilize both ports of Local Memory.

Key Concepts:

  •  Hardware Function Optimization
  •  2port BRAM Utilization
  •  Two read/write Local Memory

Keywords:

  •  #pragma HLS UNROLL FACTOR=2

Loop fusion

This example will demonstrate how to fuse two loops into one to improve the performance of a C/C++ hardware function.

Key Concepts:

  •  Hardware Function Optimization
  •  Loop Fusion
  •  Loop Pipelining

Keywords:

  •  #pragma HLS PIPELINE

Loop perfect

This nearest neighbor example is to demonstrate how to achieve better performance using perfect loop.

Key Concepts:

  • Loop perfect

Keywords:

  • #pragma HLS PIPELINE
  • #pragma HLS ARRAY_PARTITION

Loop pipeline

This example demonstrates how loop pipelining can be used to improve the performance of a hardware function.

Key Concepts:

  • Loop Pipelining

Keywords:

  • #pragma HLS PIPELINE

Loop reorder

This is a simple example of matrix multiplication (Row x Col) to demonstrate how to achieve better pipeline II factor by loop reordering.

Key Concepts:

  •  Hardware Function Optimization
  •  Loop Reorder to Improve II

Keywords:

  •  #pragma HLS PIPELINE
  •  #pragma HLS ARRAY_PARTITION

Row array 2d

This is a simple example of accessing each row of data from 2D array.

Key Concepts:

  • Row of 2D data array access

Keywords:

  • hls::stream

Shift register

This example demonstrates how to shift values in each clock cycle.

Key Concepts:

  • Hardware Function Optimization
  • Shift Register
  • FIR

Keywords:

  • #pragma HLS ARRAY_PARTITION

Systolic array

This is a simple example of matrix multiplication (Row x Col) to help developers learn systolic array based algorithm design. Note : Systolic array based algorithm design is well suited for FPGA.

Key Concepts:

  • Systolic Array

Keywords:

  • #pragma HLS PIPELINE
  • #pragma HLS ARRAY_PARTITION

Sys port

This is a simple example which demonstrates sys_port usage.

Key Concepts:

  • sys_port
  • memory interface
  • memory non-caching

Keywords:

  • #pragma SDS data sys_port
  • #pragms HLS PIPELINE
  • sds_alloc_non_cacheable

Wide memory rw

This is a simple example of vector addition to demonstrate Wide Memory Access using structure data type of 128bit wide. Based on input argument type, sds++ compiler will figure out the memory interface datawidth of hardware accelerator.

Key Concepts:

  • wide memory access
  • burst read and write
  • custom datatype

Keywords:

  • struct

Window array 2d

This is a simple example of accessing window of data from 2D array.

Key Concepts:

  • Window of 2D data array access

Keywords:

  • #pragma HLS DATAFLOW
  • #pragma HLS PIPELINE
  • #pragma HLS stream

File IO Video Processing

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing includes Motion Adaptive Noise Reduction (MANR) followed by a Sobel filter for edge detection. You can run it by supplying a 1080p YUV422 file as input with limiting number of frames to a maximum of 20 frames.

Key Concepts:

  • Video processing from file to file
  • Direct connection of HW accelerated blocks

 

Select the "File IO Video Processing" template an compile for Linux target as project te22. Copy result to root of SD card. Copy also the input file input.yuv (82 944 000 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by comman ./te22.elf ./input.yuv 20 3 ./output.yuv

The output.yuv file contains 20 frames of 1080p vido in YUV422 format with computed edges. Copy output.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Dense Optical Flow

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs LK Dense Optical Flow over two Full HD frames video file. You can run it by supplying a 1080p YUV422 file route85_1920x1080.yuv as input.

Key Concept:s

  • Video processing from file to file
  • Direct connection of HW accelerated blocks
  • Top down methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.

 

Select the "File IO Dense Optical Flow" template an compile for Linux target as project te23. Copy result to root of SD card. Copy also the input file route85_1920x1080.yuv (8 294 400 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te23.elf

The OptFlow_1920x1080.yuv file is generated and stored on the SD card. It contains one 1080p frame in YUV422 format with computed dense optical flow vectors. Copy OptFlow_1920x1080.yuv file to PC and visualise it in yuvplayer (size 1920x1080 colour YUV422).

File IO Stereo Block Matching

Linux video processing application that reads input video from a file and writes out the output video to a file. Video processing performs Stereo Block Matching to calculate depth in a single sample stereo video file desk_1280x720.yuv in YUV422 format as input and single frame Disparity_640x720.yuv in YUV422 format as output, indicating the depth of objects.

Key Concepts:

  • Video processing from file to file
  • Bottom Up methodology with detailed description in Xilinx UG1235 (v2017.1) June 20. 2017.

 

Select the "File IO Stereo Block Matching" template an compile for Linux target as project te24. Copy result to root of SD card. Copy also the input file desk_1280x720.yuv (1 843 200 bytes) to the root of the SD card. Login and cd to /media Run demo from terminal or from display+keyboard by command ./te24.elf

The Disparity_640x720.yuv file is generated and stored on the SD card. It contains one 640x720 frame in YUV422 format indicating the depth of objects. Copy Disparity_640x720.yuv file to PC and visualise it in yuvplayer (size 640x720 colour YUV422) The input file desk_1280x720.yuv can be visualised by yuvplayer (size 1280x720 colour YUV422). It contains side by side two colour frames from a stereo camera.

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