Page History
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- JTAG routing
- Boot Mode settings
- PUDC
- LED
Firmware Revision and supported PCB Revision
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Name / opt. VHD Name | Direction | Pin | Bank Power | Description | Note:|
---|---|---|---|---|---|
C_TCK | in | 30 | 3.3VIN | JTAG B2B | |
C_TDI | in | 32 | 3.3VIN | JTAG B2B | |
C_TDO | out | 1 | 3.3VIN | JTAG B2B | |
C_TMS | in | 29 | 3.3VIN | JTAG B2B | |
EN1 | in | 27 | 3.3VIN | Power Enable from B2B Connector (Positive Enable) / Used only for PGOOD feedback | |
User_LED | out | 4 | 3.3VIN | user defined or status, see LED description | 1.8V input ERR_OUT(PS_ERROR_OUT) |
N.C. | 5 | 3.3VIN | / currently_not_used1.8V input ERR_STATUS as input | ||
JTAGEN | in | 26 | 3.3VIN | Enable JTAG access to CPLD for Firmware update (zero: JTAG routed to module, one: CPLD access) | |
MODE | in | 25 | 3.3VIN | Boot Mode for Zynq/ZynqMP Devices (Flash or SD) | |
MODE0 | out | 12 | 1.8V | ZynqMP Boot Mode Pin 0 | |
MODE1 | out | 13 | 1.8V | ZynqMP Boot Mode Pin 1 | |
MODE2 | out | 14 | 1.8V | ZynqMP Boot Mode Pin 2 | |
MODE3 | out | 16 | 1.8V | ZynqMP Boot Mode Pin 3 | |
NOSEQ | inout | 23 | 3.3VIN | usage CPLD Variant depends | |
PGOOD | out | 28 | 3.3VIN | Module Power Good (only Feedback from EN1). | |
PHYPUDC_LED1 B | inout | 17 | 1.8V | ETH PHY LED1 / currently_not_usedPUD_C → external pullup | |
TCK | out | 9 | 1.8V | JTAG ZynqMP | |
TDI | out | 8 | 1.8V | JTAG ZynqMP | |
TDO | in | 10 | 1.8V | JTAG ZynqMP | |
TMS | out | 11 | 1.8V | JTAG ZynqMP | |
X0 | in | 20 | VCCO_65 | FPGA IO (FPGA Pin H1B1) / Enable User LED (negative) | output Firmware variant |
X1 | in | 21 | VCCO_65 | FPGA IO (FPGA Pin J1C1)/ Connect to User LED | output PHY_LED1 |
Functional Description
JTAG
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Note |
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NOSEQ*: Please check the carrier board documentation, before using the SD/QSPI/JTAG firmware variant on TE0820TE0821. In the most cases special carrier CPLD firmware is needed. |
PUDC
const. 1 → The I/Os will be 3-stated after power-on when PUDC is High.
Power
PGOOD is EN1. There is no additional power management controlled by CPLD.
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Firmware Variant | Blink sequence | Condition |
---|---|---|
QSPI/JTAG | *ooooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
JTAG/SD | **oooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
QSPI/SD | ****oooo *****ooo ******** | ****oooo if Boot Mod is QSPI otherwise *****ooo if NOSEQ='1' or ******** if NOSEQ='0' |
SD/QSPI/JTAG | ***ooooo | if boot mode /= JTAG otherwise const. high if NOSEQ='1' or const low if NOSEQ='0' |
Appx. A: Change History
For PCB REV01 and REV02 Documentation available on: TE0820-REV01_REV02 CPLD
Revision Changes
- REV03 REV00 to REV04
- PCB REV03 support only
X1 is input for USER LED
X0 select X0 or Firmware Blink status to User LE
blink modes for QSPI/SD firmware
- REV02 to REV03
- new Boot Mode variants
- new X0 status blink sequencing
- REV01
- copy of TE0820 CPLD Firmware
- changed PHY_LED1 in to PUDC_B out
- X0/X1 connected to other FPGA IOs
- Boot Mode variants
- X1
- Remove ERR_STATUS
Document Change History
To get content of older revision got to "Change History" of this page and select older document revision number.
Date | Document Revision | CPLD Firmware Revision | Supported PCB Revision | Authors | Description | ||||||||||||||||||||||
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| REV04REV01 | REV03REV01 |
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v.1 | REV04 | REV03 | John Hartfiel |
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v.1 | REV04 | REV03 | Page info | | created-user | created-user | |||||||||||||||||||||
All |
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