Page History

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Overview

Refer to https://shopwiki.trenz-electronic.de/de/Download/?path=Trenz_Electronic/XMODdisplay/PD/TE0790+TRM for the current downloadableonline version of this manual and additionalother technicalavailable documentation of the product.

The Trenz Electronic TE0790 is an universal USB2.0 to JTAG, UART and GPIO adapter based on the FTDI FT2232H USB2 IC. The adapter board converts signals from USB2.0 to standard serial or parallel interfaces of Embedded Systems like JTAG, SPI, I²C and UART.
The board is equipped with a programmable System Controller CPLD provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family) to control the signals of the configured interfaces. The data stream of the USB2.0 port can be also converted to 8 independent GPIO's or used as FIFO.

In order to work with Xilinx tools special order must be used, in that case the EEPROM is pre-programmed and serialized and will be recognized by all Xilinx tools (ISE/Impact/Chipscope, Vivado Programmer/SDK..).

Following table describes the possible operation modes Following table describes the possible operation modes of the TE0790 adapter board. The operation modes ared are determined by the configuration of the FT2232H , which is (done by programing the Configuration EEPROM) and the firmware implementation of the System Controller CPLD:

Table 1: Initial delivery state of programmable devices on the module.

MPSSE - FTDI protocol that is used by JTAG and SPI adapters based on FTDI devices.

Key Features

Key Features

• Xmod form-factor
  • size: 20 x 25 mm
  • M3 mounting hole
• FT2232H
  • USB2.0 port High Speed (480 Mbps) and Full Speed (12 Mbps) compatible
  • Entire USB protocol handled on the chip
  • USB2.0 to
• Xmod form-factor
  • size: 20 x 25 mm
  • M3 mounting hole
• FT2232H
  • USB2.0 port High Speed (480 Mbps) and Full Speed (12 Mbps) compatible
  • Entire USB protocol handled on the chip
  • USB2.0 to JTAG, SPI and I²C conversion provided by the IC's Multi-Protocol Synchronous Serial Engine (MPSSE)
  • USB2.0 to UART conversion
  • Channel B UART RX/TX LED's
  • Mini-USB B connector (more rigid then micro-USB)
  • 93C56 EEPROM
• Lattice XO2-256 CPLD
  • on board programmable using Lattice tools
  • 8 universal I/O pins
  • VCCIO either 3.3V or user supplied (1.8 to 3.3V)
  • RED user LED
  • 12 MHz clock from on-board Oscillator
• LDO DCDC for optional USB power
• Variable power supply of the XMOD adapter board
  
  • by Mini USB2.0 connector
  • by base-board through pin header J2
• GREEN Power-on LED
• User button
• 4 position DIP switch
  • Choose CPLD program mode
  • FTDI EEPROM disable (not implemented in PCB REV 1)
  • Use VIO same as VCC
  • Use VCC from USB

Block Diagram

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Figure 1: TE0790-02 block diagram.

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1. FTDI FT2232H IC U4
2. 2x6 Pin Header (2.54mm, female), J2
3. Mini USB B Connector J4
4. Microchip 93AA56BT-I/OT Configuration EEPROM, U10
5. DIP-switch S2
6. Push button S1
7. Lattice Semiconductor LCMXO2-256HC System Controller CPLD, U1
8. SiTime SiT8008AI-73 oscillator @12MHz, U6
9. Green LED, D1 (Power)
10. Red LED, D4 (User)
11. Red LED, D3 (UART RX)
12. Red LED, D2 (UART TX)

Initial Delivery State

Table 2: Initial delivery state of programmable devices on the module.

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The 2x6 pin header (2.54mm grid size, female) J2 have to be connected to the corresponding pin header on the target system. The signal assignment of the pin header on the adapter board depends on the configuration of the System Controller CPLD firmware.

Basic pin assignment:

Table 3: Pin header J2 signal assignment. *pin 1 on header J2

Figure 3: J2 pin header signal assignment

The signals of the FTDI FT2232H chip are not directly connected to the pin header J2 but routed to the System Controller CPLD of the adapter board, which controls and by-passes the signals to the pin header J2.

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Signal assignment on TE0790 CPLD - XMOD Standard:

Table 4: Pin header J2 signal assignment with standard configuration firmware. *pin 1 on header J2

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This is the same as the standard configuration except that UART RXD and TXD pins are swapped.

Table 5: Pin header J2 signal assignment with standard, but RXD-TXD swapped configuration firmware. *pin 1 on header J2

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On DIPFORTy, VIO Pin is connected with VDD 3.3V Pin.  UART RXD is connected to FPGA-Pin L13 and UART TXD to K15. Connect XMOD on the top-side (FPGA side) of the PCB.

Table 6: Pin header J2 signal assignment with DIPFORTy firmware.

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By programing the firmware of the SC CPLD and special EEPROM configurations further further functionalities are available of the FTDI chip which converts signals from USB2.0 to a variety of standard serial and parallel interfaces. Refer to the FTDI data sheet to get information about the capacity of the FT2232H IC.

Configuration EEPROM

In order to work with Xilinx tools special order must be used, in that case the EEPROM is pre-programmed and serialized and will be recognized by all Xilinx tools (ISE/Impact/Chipscope, Vivado Programmer/SDK..).

The external EEPROM can be used to customize the TE0790 adapter board by setting numerous parameters of the FT2232H IC, enabling different functionalities and configuring serial or parallel interfaces.

The EEPROM is programmable in-circuit over USB using a utility program called FT_PROG available from FTDI’s web site (www.ftdichip.com).

System Controller CPLD

The System Controller CPLD (U1) is provided by Lattice Semiconductor LCMXO2-256HC (MachXO2 Product Family). The  The SC-CPLD is the central system management unit where essential control signals are logically linked by the implemented logic in CPLD firmware, which generates output signals to control the system, the on-board peripherals and the interfaces.

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The internal routing of the signals on the System Controller CPLD between the USB2.0 interface and pin header J2  J2 depends on its configured firmware. Refer to the Resources Site of the TE0790 CPLD can be set into JTAG chain via  S2-1 DIP Switch. Refer to the TE0790 CPLD Firmware for more information about the currently available System Controller CPLD firmware and for download.

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The DIP-switch S2 is to set different modes of powering the on-board peripherals and their components, the I/O supply voltages .Further functionalities are to secure the EEPROM content and to enable configuring programming the SC adapter board CPLD by JTAG interface:

Table 7: DIP-switch S2 setting description.

The voltages 3.3V (VCC) and VIO (variable SC CPLD I/O-voltage) can be configured by the DIP-switches S2-3 and S2-4:

Table 8: DIP-switch S2 power setting description.

User Push Button

• *max. 100mA for external components (It's not recommended to supply FPGA Module)
    Attention: Do not use this setting, if base power supply is connected to this pins!  For more details see Power supply of the adapter board  section.
• **view of XMOD

Table 8: DIP-switch S2 power setting description.

User Push Button

The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by The user push button S1 directly connected to the SC CPLD manipulates pin G of the pin header J2 by driving it to GND.

On-board LEDs

The on-board LEDs indicates system status data transmission activities:

Table 9: On-board LEDs.

Power and Power-On Sequence

Power supply of the adapter board

The adapter on-board's peripherals are powered XMOD can be powered via USB or with 3.3V as supply voltage. If 3.3V (VCC and VIO) is supplied only by the LDO DCDC U3 (on J2 pins, depending on DIP-switch settings. Max. ~100mA for external components are available on J2 3.3V Pin, if the power supply via USB is used.

Following diagram shows how the settings of the DIP-switches S2-3 and S2-4 OFF), the I/O-pins of header J2 deliver max. ~100mA.If module is powered from base then S2-4 (and most likely S2-3 (VIO) too) must be OFF.determines the configuration of the on-board voltages:

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Figure 4: TE0790 on-board voltages configuration

Power Rails

 Table 10: Module power rails.

Variants Currently In Production

Table 11: Module variants.

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Technical Specifications

Absolute Maximum Ratings

Table 12: Module absolute maximum ratings.

Recommended Operating Conditions

Table 13: Module recommended operating conditions.

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• Module size: 24,65mm × 20,02mm.  Please download the assembly diagram for exact numbers.

• Mating height with standard pin headers: 89.5 mm.

• PCB thickness: 1.75 6 mm.

• Highest part on PCB: approx. 8.75 7 mm. Please download the step model for exact numbers.

All dimensions are given in millimeters and mil.

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Figure 35: Module physical dimensions drawing.

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Hardware Revision History

Table 14: Module hardware revision history.

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Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Figure 46: Module hardware revision number.

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Date

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Revision

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Contributors

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Description

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Table 15: Document change history.

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