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Template Revision 2.112

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"
  • Carrier: TRM Name usually "TEB Series Name" +TRM
    Example: "TEB0728 TRM"

...

The Trenz Electronic TEBA0714 is a carrier for Trenz Electronic module TE0714 which is an industrial - grade ... module ... based on Xilinx ...module integrated with Xilinx Artix 7. 

Refer to http://trenz.org/teba0714-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly optionsKey optionsKey Features'  must be split into 6 main groups:
  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • Module:
    • Trenz TE0714 Modul CarrierTemperature:
  • On Board:
    • 2 x User LEDs (Red, Green)
    • 1 x DONE LED (Red)
  • Interface:
    • 2 x Pin - Header 50 50 Pol. (FPGA Bank I/Os and Power)
    • 2x Samtec 100 Pin LSHM Series Connectors
    • 2 x Pin-Header for FPGA Bank Power
    • 1 x XMOD JTAG/UART Adapter (TE0790) Pin-Header
    • 1 x Pin - Header 16 Pol. (JTAG, MGT-CLK, Boot Mode, XADC, I/O's)
    • 1 x Pin - Header 10 Pol. (Ein-/ und AusgängeFPGA Bank I/Os and Power)
    • 1 x SFP+ Connectors
  • Power:
    • 1 x LDO Regulator
    • 3.3V  Nominal Power supply
  • Dimension: 
    • 46 mm × 75
    Dimension: 30 mm x 40
    • mm

Block Diagram

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add drawIO object here.

Note
For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .



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titleTEBA0714 block diagram


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Main Components

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Notes :
  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note
For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



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titleTEBA0714 main components


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  1. 6-SMT pin header J26 for selecting PL-bank I/O voltage6-, J26
  2. SMT pin header, J27 for selecting XMOD/JTAG VCCIO
  3. Samtec Razor Beam™ LSHM-150 B2B connector, JM1
  4. Board to Board  (B2B) Connector, JM1
  5. Board to Board  (B2B) Connectorr, JM2Samtec Razor Beam™ LSHM-150 B2B connector, JM2
  6. XMOD header, JX1
  7. Voltage Regulator, U1
  8. User Red LED, D2
  9. User Green LED, D1 (redRed)
  10. SFP+ Connector, J1
  11. User Red LED D3, indicating FPGA's 'Programming DONE'-signal, D3
  12. 50 - pin header solder pads J20 for access to SoM's PL I/O-banks (LVDS pairs possible)
  13. 16-pin header solder pads J3, JTAG/UART header with ADC and MGT clock input
  14. 10-pin header solder pads J4 for access to SoM's PL I/O-banks (LVDS pairs possible)
  15. (Not assembled),  J20
  16. 16 pin header (Not assembled),  J3,
  17. 10-pin header (Not assembled), J4 
  18. 50-pin header (Not assembled), J1750-pin header solder pads J17 for access to SoM's PL I/O-banks (LVDS pairs possible)

Initial Delivery State

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Notes :Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.If there is no components which might have initial data ( possible on carrier) you must keep the table empty
  • VCCIO voltage selection jumpers are all set to 1.8 V.
  • Pin headers (not soldered to the board, but included in the package as separate component)


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titleInitial delivery state of programmable devices on the module

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Storage device nameContentNotes
---------


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

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titleBoot process.

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SignalMODE Signal StateBoot ModeNote
BOOTMODE
high or open
0Slave SelectMAP
1Master SPI
, x4 Mode

low or ground

Slave Selects MAP




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titleReset process.

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SignalB2BSignal StateNote
PROG_BJM1-94Active LowClear FPGA configuration (falling edge) configuration  and initiate a new configuration sequenz (next rising edge).


Signals, Interfaces and Pins

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Notes :
  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number Number of I/O signals and Interfaces connected to the B2B connector:

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titleGeneral PL I/O to B2B connectors information

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B2B ConnectorInterfaceNumber of I/ONotes
JM1



User I/O52 Single ended, 27 Differential-
MGT lanes4 Differential, 2 lanes
MGT reference clock input2 Single ended, 1 Differential
JTAG4 Single ended
SoM control signals2 Single ended'PROG_B', ' DONE'
JM2User I/O36 Single ended or 18 differential-
SFP+ Interface control signals8 Single ended
QSPI interface6 Single ended
UART interface2 Single ended
User LEDs2 Single endedRed, Green
SoM control signals1 Single ended'BOOTMODE'

...


On-board Pin Header

TEBA0714 is equipped with four pin headers J17, J20, J3 and J4 which are not assembled on the board, in case of need customer can solder the pins and have access to the signals in the following tableJTAG access to the TEBA0714 SoM through B2B connector JM1.

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titleJTAG pins connectionGeneral I/O to Pin headers information

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JTAG Signal

B2B Connector
TCKJM1-90
TDIJM1-86
TDOJM1-88
TMSJM1-92

On-board Connectors

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

Pin HeaderInterfaceNumber of I/ONotes
J17



User I/O36 Single ended, 18 DifferentialModule FPGA Bank 14
SPI interface6 Single ended-
Power4 Single ended3.3V, V_CFG
J20User I/O42 Single ended or 21 differentialModule FPGA Bank 34
Power4 Single ended3.3V, V_CFG
User LEDs2 Single endedRed, Green
SoM control signals1 Single ended'BOOTMODE'
J3JTAG 4 Single ended
UART2 Single endedB14_L25, B14_L0
ADC2 Single ended
Clock2 Single ended, 1 Differential
Power4 Single ended3.3V, V_CFG
Control Signals2 Single endedBOOTMODE, PROG_B
J4User I/O6 Single ended or 3 differential
Power2 Single ended3.3V, 3.3V_OUT


JTAG Interface Base

JTAG access to the mounted SoM is provided through B2B connector JM1 and JM2 and is also routed to the XMOD JTAG/UART header JX1.

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titleJTAG pins connection

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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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On board Connectors

...

anchorTable_OBP_MIOs
titleMIOs pins

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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titleOn board peripherals
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Chip/InterfaceDesignatorNotes

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

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anchorTable_OBP_SPI
titleQuad SPI interface MIOs and pins
XMOD Header PinSchematicB2B ConnectorPin HeaderNote
AB14_L25JM2-97J3-4UART Transfer
BB14_L0JM2-99J3-7UART Receive
EBOOTMODEJM2-100J3-9
GPROG_BJM1-94J3-11
CTCKJM1-90J3-4
DTDIJM1-86J3-10
FTDOJM1-88J3-8
HTMSJM1-92J3-12
3.3V3.3VJM1-97,99J3,J4,J17,J20Nominal Input Voltage
VIOV_CFG-J17-45Configuration Voltage


The DIP-switch S2 on XMOD Adapter TE0790 must be set as the following table.

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titleJTAG pins connection

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titleI2C interface MIOs and pins
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MIO PinSchematicU? PinNotes
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titleI2C Address for RTC

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MIO Pin
S2
I2C Address
Status
Designator
Description
Notes
Notes      

...

1ONUpdate Mode JTAG access to SC CPLD only
2OFFMust be in OFF state always
3OFF3.3V  is inputsupplied from pin headers externally
4OFFVIO is inputsupplied from pin header externally


SFP+ Connector

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titleSFP+ Connector Information
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titleI2C EEPROM interface MIOs and pins

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MIO
Pin
SchematicU?? PinNotes
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titleI2C address for EEPROM
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MIO PinI2C AddressDesignatorNotes

LEDs

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anchorTable_OBP_LED
titleOn-board LEDs
Connected toNotes
VCCR3.3V
VCCT3.3V
VREFGND
TD+/TD-MGT TXMGT Lane
RD+/RD-MGT RXMGT Lane
TX/FAULTSFP0_TX_FAULSFP_CTRL
TX/DISABLESFP0_TX_DISSFP_CTRL
MOD-DEF2SFP0_SDASFP_CTRL
MOD-DEF1SFP0_SCLSFP_CTRL
MOD-DEF0SFP0_MT_DEF0SFP_CTRL
RS0/RS1SFP0_RS0_1SFP_CTRL
LOSSFP0_LOSSFP_CTRL


SMT Pin Headers

There are two SMT Pin Headers, J26-J27.
J26 is available to choose voltage level for VCCIO34 (FPGA Bank 34) and J27 is provided to set the voltage level of V_CFG (Configuration Voltage). In order to set the voltage level, you should connect it to the corresponding pin with the target value voltage.

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titleSMD Connector Information

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SMT Pin HeaderVCCIO/VCCVoltage LevelNotes
J26VCCIO34

1.8V
2.5V
3.3V3.3V_OUT
J27V_CFG

1.8V
2.5VV_CFG0
3.3V3.3V_OUT


On-board Peripherals

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Notes :
  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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DDR3 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: 
  • Supply voltage:
  • Speed: 
  • NOR Flash
  • Temperature: 

Ethernet

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titleEthernet PHY to Zynq SoC connectionsOn board peripherals

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BankSignal NameETH1ETH2Signal Description

...

Chip/InterfaceDesignatorNotes
LEDsD1...3


LEDs

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titleOsillatorsOn-board LEDs

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DesignatorColor
Description
Connected to
Frequency
Active LevelNote
MHz
D1GreenGLEDActive High
D2RedRLEDActive High
D3RedDONEActive LowDONE pin
MHzKHz


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:
  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note
For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx A for system startup is recommended3A for system startup is recommended.

The on-board voltages of the carrier board will be powered up with an external power-supply with nominal voltage of 3.3V.

Power Consumption

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titlePower Consumption

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Power Input PinTypical Current
VIN3.3V* TBD*


* TBD - To Be Determined

Power Distribution Dependencies

Determined

Power Distribution Dependencies

3.3V can be supplied through Pin Headers on specific pins. 

Figure
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titlePower Distribution


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Power-On Sequence

There is no specific power-on sequence. After power on, the module and carrier will be powered on.

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titlePower Sequency


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Voltage Monitor Circuit

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titleVoltage Monitor Circuit
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Power Rails

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titleModule power rails.

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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

Bank Voltages

Notes

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Power Rail Name

B2B , JM1 Pin

B2B JM2 Pin

Pin Header J17Pin Header J20Pin Header J3Pin Header J4DirectionNotes
3.3V99,97-5, 465, 4655Input
1.8V-18----InputComes from Module
3.3V_OUT8354---6Output
VCCIO3461--45--OutputVariable voltage level
V_CFG53-----InputVariable voltage level
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titleZynq SoC bank voltages.
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Bank          

Schematic Name

Voltage