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  • Xilinx Zynq-7000 XC7Z045-2FFG900I SoC
  • Rugged for shock and high vibration
  • Large number of configurable I/Os are provided via rugged high-speed stacking strips
  • Dual ARM Cortex-A9 MPCore
    • 1 GByte RAM (32bit wide DDR3) connected to PS
    • 2 GByte RAM (64bit wide DDR3) connected to PL
    • 32 MByte QSPI Flash memory
    • Hi-Speed USB2 ULPI transceiver PHY
    • Gigabit (10/100/1000 Mbps) Ethernet transceiver PHY
    • 4 GByte eMMC (optional up to 64 GByte)
  • Lattice MachXO2 HC 4000 System Controller CPLD
    • 40 GPIO's available to user on B2B connector
  • MAC-address EEPROM
  • Serial user EEPROM
  • Temperature compensated RTC (real-time clock)
  • Si5338A programmable quad PLL clock generator for GTX transceiver clocks
  • Plug-on module with 3 x 160-pin high-speed strips
    • 16 GTX high-performance transceiver
    • 4x GT transceiver clock inputs
    • 254 166 FPGA I/O's (125 83 LVDS pairs)
  • On-board high-efficiency switch-mode DC-DC converters
  • System management
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
  • User LED

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titleFigure 1: TE0783-01 block diagram


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Storage device nameContentNotes
24LC128-I/ST EEPROM not not programmedUser content

24AA025E48 EEPROM

User content not programmed

Valid MAC Address from manufacturer
Si5338A OTP Areanot programmed-
eMMC Flash MemoryEmpty, not programmedExcept serial number programmed by flash vendor

SPI Flash OTP Area

Empty, not programmed

Except serial number programmed by flash vendor

SPI Flash Quad Enable bit

Programmed

-

SPI Flash main array

demo design

-

eFUSE USER

Not programmed

-

eFUSE Security

Not programmed

-

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The TE0783 boot mode is selected by the pin 'CPLD_GPIO3' of the SC CPLD, which is connected to B2B pin J2-16 to either boot from the on-board QSPI Flash memory U38 or SD IO interface. See section Bootmode in the TE0783 SC CPLD reference Wiki page.

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Special purpose pins are connected to System Controller CPLD (U32) and have following default configuration:

Pin NameDirectionFunctionDefault Configuration
EXT_IO1 ... EXT_IO40in / outuser GPIO on B2Bsee current CPLD firmware
BOOTMODEininsignal forwarded to MIO9 and currently used as UART RX line
CONFIGXinoutsignal forwarded to MIO8 and currently used as UART TX line
NRST_INinnRESET inputexternal Board Reset
M_TDOoutCPLD JTAG interface



-
M_TDIin
M_TCKin
M_TMSin
JTAGENBinenable JTAGpull high for programming SC CPLD firmware
ETH1_RESEToutreset GbE PHY U18see current SC CPLD firmware
OTG-RSToutreset USB2 PHYs
U4 and U8
see current SC CPLD firmware
DONEinZynq control signalPL configuration completed
PROG_BoutPL configuration reset signal
PS_PORoutPS power-on reset
BM2/MIO4out

Bootmode Pin: SD or QSPI

MIO14inuser MIO pins

currently used as UART interface
MIO15out
LED2outRed LED D1 status signalsee current CPLD firmware
CPLD_GPIO0 ... CPLD_GPIO3in / outuser GPIO on B2BCPLD_GPIO3 used for Boot Modesee current CPLD firmware
FPGA_CPLD1 ... FPGA_CPLD4in /outuser GPIO to FPGA bank 9see current SC CPLD firmware
EN_1VoutPower controlenable signal DCDC U13 '1V'
PG_ALLin

power good signal all voltages powered up properly

→ Green LED D2 lights up.

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GbE PHY connection:

----
PHY PINZynq PS / PLSystem Controller CPLDNotes
MDC/MDIOMIO52, MIO53-
LED0Bank 9, Pin AC18-
LED1Bank 9, Pin AC19-
Interrupt--not connected
CLK125--125 MHz clock output not connected
CONFIG--When pin connected to GND, PHY Address is strapped to 0x00 by default
RESETnMIO7ETH1_RESET33 (MIO7) → voltage level translator U30 → ETH1_RESET
RGMIIMIO16..MIO27-
MDI--on B2B J2 connector

Table 9: General overview of the Gigabit Ethernet1 PHY signals

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USB2 PHY connection:

OTG_RESET33-
PHY PinZynq PS / PLCPLDB2B Connector J2Notes
ULPIMIO28..39--Zynq USB0 MIO pins are connected to the PHY
REFCLK---52MHz from on board oscillator (U7)
REFSEL[0..2]---000 GND, select 52MHz reference Clock
RESETBMIO0-OTG-RESET33 → voltage level translator U30 → OTG-RESET
CLKOUTMIO36-Connected to 1.8V selects reference clock operation mode
DP,DM--USB1_D_P, USB1_D_NUSB Data lines
CPEN--VBUS1_V_ENExternal USB power switch active high enable signal
VBUS--USB1_VBUSConnect to USB VBUS via a series resistor. Check reference schematic.
ID--OTG1_IDFor an A-Device connect to ground, for a B-Device left floating

Table 10: General overview of the Gigabit Ethernet2 PHY signals

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By default TE0783-01 module has two 16-bit 16bit wide IM (Intelligent Memory) IM4G16D3FABG-125I DDR3L SDRAM (DDR3-1600 Speedgrade) connected to the PS DDR memory bank 502, the chips are arranged into 32bit wide memory bus providing total of 1 GBytes of on-board RAM.

Another 4 chips are arranged into 64bit wide memory bus prodivding total of 2 GByte on-board RAM connected to the PL HP banks 34, 35 ,and 36.

Quad SPI Flash Memory

One quad SPI compatible serial bus Flash memory (U38) for FPGA configuration file storage is provided by Spansion S25FL256SAGBHI20 with 256 Mbit (32 MByte) memory density. After configuration completes the remaining free memory can be used for application data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths to be used. The maximum data transfer rate depends on the bus width and clock frequency.

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SignalFrequencyNotes
IN1/IN2user

External clock signal supply from B2B connector J3, pins J3-38 / J3-40

IN3

25.000000 MHz

Fixed input clock signal from reference clock generator SiT8008BI-73-18S-25.000000E (U3)

IN4-LSB of the default I2C address, wired to ground mean address is 0x70

IN5

-

Not connected

IN6

-

Wired to ground
CLK0 A/B

-

reference clock 0 of Bank 112 GTX

CLK1 A/B

-

reference clock 1 of Bank 111 GTX

CLK2 A/B

-

reference clock 0 of Bank 110 GTX

CLK3 A/B-reference clock 1 of Bank 109 GTX

Table 1412: General overview of the on-board quad clock generator I/O signals

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Clock SourceSchematic NameFrequencyClock Destination
SiTime SiT8008AI oscillator, U61PS_CLK33.333333 MHzZynq SoC U1, pin A22
SiTime SiT8008BI SiT8008AI oscillator, U21U33-PL_CLK2533.000000 333333 MHzQuad PLL clock generator U2, pin 3Zynq SoC U1, pin AA18
Microchip DSC1123 oscillator, U15MIG_SYS_CLK_P / MIG_SYS_CLK_N200.0000 MHzZynq SoC U1, pins H9, G9
SiTime SiT8008BI oscillator, U3-25.000000 MHzQuad PLL clock generator U2, pin 3
Microchip DSC1123 oscillator, U31B9_CLK_P, B9_CLK_N125.0000 MHzZynq SoC U1, pins AD18, AD19
SiTime SiT8008AI oscillator, U7-52.000000 MHzUSB2 PHYs U4 and U8, pin 26
SiTime SiT8008BI oscillator, U11-25.000000 MHzGbE PHYs U18 and U20, pin 34

Table 1513: Reference clock signals

On-board LEDs

Exact function is defined by SC CPLD firmware
LEDColorConnected toDescription and Notes
D1RedSystem Controller CPLD U14U32, bank 30Indicates power-up sequence completed.
D2GreenSystem Controller CPLD U14U32, bank 32Exact function is defined by SC CPLD firmware.

Table 1614: On-board LEDs

Power and Power-on Sequence

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Power InputTypical Current
VINTBD*
C3.3VTBD*

Table 1715: Power consumption


 * TBD - To Be Determined soon with reference design setup.

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The Trenz TE0783 SoM is equipped with two quad DC-DC voltage regulators to generate required on-board voltage levels 1V, 3.3V, 1.8V, 1.2V_MGT, 1V_MGT. Additional voltage regulators are used to generate voltages 3.3V_SB, 1.5V, VTT, VTTREF for PS and PL memory bank, 1.8V_MGT and VCCAUX_IO.

The power supply voltage 'C3.3V' of System Controller CPLD of the SoM have to be externally supplied with 3.3V nominal.

There are following dependencies how the initial voltages of the power rails on the B2B connectors are distributed to the on-board DC-DC converters, which power up further DC-DC converters and the particular on-board voltages:

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titleFigure 3: TE0783-01 Power Distribution Diagram


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See also Xilinx datasheet DS191 for additional information. User should also check related base board documentation when intending base board design for TE0783 module.

Power-On Sequence

module.

Power-On Sequence

Power-on sequence is handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

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titleFigure 4: TE0783-01 Power-on Sequence Diagram


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Voltage Monitor Circuit

The voltages '1V' and '3.3V' are monitored by the voltage monitor circuit U27, which generates the PS_POR reset signal if monitored voltages have transient interruptionsPower-on sequence is handled by the System Controller CPLD using "Power good"-signals from the voltage regulators:

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titleFigure 45: TE0783-01 Power-on Sequence DiagramVoltage Monitor Circuit


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Power Rails

Power Rail Name on B2B ConnectorJ1 PinsJ2 PinsJ3 PinsDirectionNotes
VIN-165, 166, 167, 168-Inputexternal power supply voltage
C3.3V-147, 148-Inputexternal 3.3V power supply voltageNormally leave unconnected
3.3V-

111, 112, 123, 124, 135 136

169, 170, 171, 172

-Outputinternal 3.3V voltage level
1.8V169, 170, 171, 172--Outputinternal 1.8V voltage level
EXT_IO_VCC99, 100--InputSC CPLD bank 1, 2 and 4 voltage
VCCIO_10--99, 100Inputhigh range I/O bank voltage
VCCIO_11--159, 160Inputhigh range I/O bank voltage
VCCIO_12-159, 160-Inputhigh range I/O bank voltage
VCCIO_13-99, 100-Inputhigh range I/O bank voltageVCCIO_3399, 100--Inputhigh performance I/O bank voltage
VCCIO_34159, 160--Inputhigh performance I/O bank voltage
VBAT_IN--124Inputbackup battery voltage

Table 1816: Module power rails

Bank Voltages

33 V
BankSchematic NameVoltageRangeNotes
0-3.3 V-FPGA configuration
502-1.5 V-DDR3-RAM port
109 / 110 / 111 / 112-1.2 V-MGT
500 / -3.3 V-PS MIO banks
501-1.8V-PS MIO banks
9 (HR)-13.8 3 V1.2V to 3.3V--ETH2 RGMII
10 (HR)VCCIO_10user1.2V to 3.3V-
11 (HR)VCCIO_11user1.2V to 3.3V-
12 (HR)VCCIO_12user1.2V to 3.3V-
13 (HR)VCCIO_13user1.2V to 3.3V-
33 (HP)VCCIO_33user1.5V_PL1.2V to 1.8V-5 V-64bit DDR3L SD-RAM
34 (HP)VCCIO_34user1.5V_PL1.2V to 1.8V5 V-
35 (HP)-1.8 V5V_PL1.2V to 1.8VHyper-RAM, Ethernet, I²C5 V-

Table 17Table 19: Module I/O bank voltages

See Xilinx Zynq-7000 datasheet DS191 for the voltage ranges allowed.

Board to Board Connectors

.

Board to Board Connectors

Include Page
8.5 x 8.5 SoM QSH and QTH B2B Connectors
8.5 x 8.5 SoM QSH and QTH B2B Connectors
The TE0783 SoM has three 160-pin double-row ASP-122952-01  Samtec connectors on the bottom side which mate with ASP-122953-01 Samtec connectors on the baseboard. Mating height is 5 mm.

Variants Currently In Production

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Parameter

MinMax

Units

Notes

VIN supply voltage

-0.3

15

V

LTM4644 datasheet
C3.3V VBAT supply voltage-0.33.6VLTM4644 TPS780180 datasheet
PS I/O supply voltage, VCCO_PSIO-0.53.6VXilinx document DS191
PS I/O input voltage-0.4VCCO_PSIO + 0.55VXilinx document DS191
HP I/O bank supply voltage, VCCO-0.52.0VXilinx document DS191
HP I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS191
HR I/O bank supply voltage, VCCO-0.53.6VXilinx document DS191
HR I/O bank input voltage-0.55VCCO + 0.55VXilinx document DS191Reference Voltage pin-0.52VXilinx document DS191
Differential input voltage-0.42.625VXilinx document DS191
MGT reference clocks absolute input voltage-0.51.32VXilinx document DS191
MGT absolute input voltage-0.51.26VXilinx document DS191

Voltage on SC CPLD pins

-0.5

3.75

V

Lattice Semiconductor MachXO2 datasheet

Storage temperature

-40

+85

°C

See eMMC MTFC4GMVEA eMMC MTFC4GACAJCN datasheet

Table 2018: Module absolute maximum ratings

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ParameterMinMaxUnitsNotes
VIN supply voltage11.41412.6VSee LTM4644 datasheet12V nominal power supply voltage
VBAT C3.3V supply voltage32.3235.4655VSee LCMXO2-256HC, LTM4644 TPS780180 datasheet
PS I/O supply voltage, VCCO_PSIO1.7103.465VXilinx document DS191
PS I/O input voltage–0.20VCCO_PSIO + 0.20VXilinx document DS191
HP I/O banks supply voltage, VCCO1.141.89VXilinx document DS191
HP I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS191
HR I/O banks supply voltage, VCCO1.143.465VXilinx document DS191
HR I/O banks input voltage-0.20VCCO + 0.20VXilinx document DS191
Differential input voltage-0.22.625VXilinx document DS191
Voltage on SC CPLD pins-0.33.6VLattice Semiconductor MachXO2 datasheet
Operating Temperature Range-4085°CXilinx document DS191, industrial grade Zynq temperarure range

Table 2119: Recommended operating conditions

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Scroll Title
anchorFigure_56
titleFigure 56: Module physical dimensions drawing

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DateRevision

Notes

PCN LinkDocumentation Link
-01first production release-TE0783-01

Table 2220: Hardware revision history table

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anchorFigure_67
titleFigure 67: Module hardware revision number

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Date

Revision

Contributors

Description

Page info
modified-date
modified-date
dateFormatyyyy-MM-dd

Page info
infoTypeCurrent version
dateFormatyyyy-MM-dd
prefixv.
typeFlat

Page info
infoTypeModified by
dateFormatyyyy-MM-dd
typeFlat

  • linked B2B
2018-08-07v.18Ali Naseri
  • Initial version
--all

Page info
infoTypeModified users
typeFlat
showVersionsfalse

  • --

Table 21Table 23: Document change history

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