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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
Date | Version | Changes | Author |
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2023-12-14 | 3.1.17 | - updated according to Vivado 2023.2
| ma | 2023-06-13 | 3.1.16 | - Design flow:
- added alternative programming files in Petalinux
- added chapter FSBL Patch in Software Design - Petalinux
| ma | 2023-06-01 | 3.1.15 | - removed u-boot.dtb from Design flow
| ma | 2023-06-01 | 3.1.14 | - expandable lists for revision history and supported hardware
| wh | 2023-05-25 | 3.1.13 | - updated according to Vivado 2022.2
| ma | 2023-02-08 | 3.1.12 | - removed content of
- Special FSBL for QSPI programming
| ma | 2022-08-24 | 3.1.11 | - Modification from link "available short link"
| ma | 2022-01-25 | 3.1.10 | - removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 2022-01-14 | 3.1.9 | - extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
| jh | 2021-06-28 | 3.1.8 | - added boot process for Microblaze
- minor typos, formatting
| ma | 2021-06-01 | 3.1.7 | | jh | 2021-05-04 | 3.1.6 | - removed zynq_ from zynq_fsbl
| ma | 2021-04-28 | 3.1.5 | - added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-27 | 3.1.4 | - Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
| ma |
| 3.1.3 | | ma |
| 3.1.2 | - minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.scr description
- added USB for programming
| ma |
| 3.1.1 | - swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
| ma |
| 3.1 | - Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
|
|
| 3.0 | - add fix table of content
- add table size as macro
- removed page initial creator
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
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Overview
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Zynq PS Design with DDR Less FSBL Example.
Refer to http://trenz.org/te0722-info for the current online version of this manual and other available documentation.
Key Features
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Notes : - Add basic key futures, which can be tested with the design
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Excerpt |
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- Vivado 2023.2
- UART
- I2C
- SD
- Modified FSBL for DDR Less Zynq + small app with LED+Sensor and SD Card access
- Special FSBL for QSPI programming
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Revision History
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Notes : - add every update file on the download
- add design changes on description
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Date | Vivado | Project Built | Authors | Description |
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2024-03-25 | 2023.2 | TE0722-test_board_noprebuilt-vivado_2023.2-build_4_20240325150206.zip TE0722-test_board-vivado_2023.2-build_4_20240325150206.zip | Waldemar Hanemann | | 2023-02-13 | 2021.2 | TE0722-test_board_noprebuilt-vivado_2021.2-build_20_20230214143311.zip TE0722-test_board-vivado_2021.2-build_20_20230214143311.zip | Waldemar Hanemann | | 2020-04-16 | 2019.2 | TE0722-test_board_noprebuilt-vivado_2019.2-build_10_20200416064916.zip TE0722-test_board-vivado_2019.2-build_10_20200416064756.zip | John Hartfiel | | 2019-05-22 | 2018.3 | TE0722-test_board-vivado_2018.3-build_05_20190522113216.zip TE0722-test_board_noprebuilt-vivado_2018.3-build_05_20190522113228.zip | John Hartfiel | - split FSBL into 2 templates, one with and one without Sensor+LED access example app
| 2019-05-14 | 2018.3 | TE0722-test_board-vivado_2018.3-build_05_20190510163659.zip TE0722-test_board_noprebuilt-vivado_2018.3-build_05_20190510163900.zip | John Hartfiel | - TE Script update
- rework of the FSBLs
- DDR LESS, Device ID, Sensor+LED access
- VIO for RGB access
| 2018-08-14 | 2018.2 | TE0722-test_board-vivado_2018.2-build_02_20180815123557.zip TE0722-test_board_noprebuilt-vivado_2018.2-build_02_20180815123610.zip | John Hartfiel | |
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Release Notes and Know Issues
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
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title | Known Issues |
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Issues | Description | Workaround | To be fixed version |
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QSPI Flash Programming failed with 19.2 | Depending on Flash content Flash programming failed with provided fsbl_flash (Xilinx AR# 70548 ) 2019.2 version | - Option1:
- In case Flash is empty, use fsbl_flash on programming GUI
- In case Flash is programmed use normal fsbl on programming GUI
- Option2: use in both case fsbl_flash on programming GUI and Vivado LabTools 2018.3
- see also AR#00002 and TE0722-Recovery
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Requirements
Software
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Notes : - list of software which was used to generate the design
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Software | Version | Note |
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Vitis | 2023.2 | needed, Vivado is included in Vitis installation |
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Hardware
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Notes : - list of software which was used to generate the design
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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anchor | Table_HWM |
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title | *used as reference |
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orientation | portrait |
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Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
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TE0722-01 | 10 | REV01 | 0GB | 16MB | NA | NA | NA | TE0722-02 | 10 | REV02 | 0GB | 16MB | NA | NA | NA | TE0722-02I * | 10_i | REV02 | 0GB | 16MB | NA | NA | NA | TE0722-02IC7 | 10_i_c7 | REV02 | 0GB | 16MB | NA | "without SD" | NA | TE0722-02-07S-1C | 7s | REV02 | 0GB | 16MB | NA | NA | NA | TE0722-04-41C-4-A | 10 | REV04 | 0GB | 16MB | NA | NA | NA | TE0722-04-41I-4-A* | 10_i | REV04 | 0GB | 16MB | NA | NA | NA |
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Additional HW Requirements:
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Additional Hardware | Notes |
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TE0790(for AMD) or other JTAG programmer | for JTAG, UART | external 3.3V power supply |
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Content
For general structure and of the reference design, see Project Delivery - AMD devices
Design Sources
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Type | Location | Notes |
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
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Additional Sources
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
|
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of AMD Software for the same Project.
Design Flow
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Note |
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
---|
Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Code Block |
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language | bash |
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theme | Midnight |
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title | _create_win_setup.cmd/_create_linux_setup.sh |
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
optional for manual changes: Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") |
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TE::hw_build_design -export_prebuilt |
Info |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
- Generate Programming Files with Vitis
Run on Vivado TCL:
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") |
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TE::sw_run_vitis -all |
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv"
(alternative) Start Vitis with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
Projects contains 3 FSBL template: zynq_fsbl (FSBL modified for DDR Less application → use for Boot.bin), zynq_fsbl_app (FSBL modified for DDR Less application and with demo app included → create Boot with this FSBL and Bitstream only), zynq_fsbl_flash(FSBL modified for Flash programming →FSBL which must be selected separately to program Flash)
Info |
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TE0722 is without DDR, so special FSBL (sources on reference designs) is needed, see also: DDR less ZYNQ Design |
Launch
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Note: - Programming and Startup procedure
|
Basic Information, see TE0722 Getting Started
Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/Vitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info |
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Set Board to JTAG Bootmode. Short pins of J4.
Option for Boot.bin on QSPI Flash
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type on Vivado TCL Console:
Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script programs BOOT.bin on QSPI flash) |
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TE::pr_program_flash -swapp zynq_fsbl_app
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SD-Boot mode
Xilinx Zynq devices in CLG225 package do not support SD Card boot directly from ROM bootloader. Use QSPI for primary boot and SD for secondary boot only. See also Xilinx AR#66846
JTAG
The JTAG Bootmode can be set on the newer pcb revisions, REV04+ (short both pins of J4)
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Power On PCB
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|
1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream 3. FSBL starts application (included into the FSBL Code) |
Standalone Application
Note: UART over J2 is used, this is only available, if PL part is configured with correct UART connection.
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info |
---|
Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
- Output:
- Default output appears only a few seconds. Reboot device: force ResN pin to GND for short time, location see: TE0722 Getting Started
SD card FAT32 Format should be inserted for SD access.
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)
- Control:
- Enable/Disable RGB LED Counter (default on)
- Enable/Disable different colors (default all off) - set to '1' to enable RGB LED
Scroll Title |
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anchor | Figure_VHM |
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title | Vivado Hardware Manager |
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System Design - Vivado
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Block Design
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border | true |
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diagramName | TE0722_Blockdiagramm_infolay |
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simpleViewer | false |
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width | 600 |
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links | auto |
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tbstyle | top |
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lbox | true |
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diagramWidth | 2580 |
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revision | 1 |
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PS Interfaces
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anchor | Table_PSI |
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title | PS Interfaces |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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Type | Note |
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DDR | Disabled! | QSPI | MIO | SD | MIO | UART0 | EMIO | I2C1 | MIO | GPIO | MIO | SWDT0 | EMIO | TTC0..1 | EMIO |
|
Constraints
Basic module constraints
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language | ruby |
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title | _i_bitgen_common.xdc |
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#
# Common BITGEN related settings for TE0722
#
set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 3.3 [current_design]
set_property CFGBVS VCCO [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLUP [current_design] |
Design specific constraints
Code Block |
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language | ruby |
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title | _i_uart_j2xmod.xdc |
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set_property PACKAGE_PIN K15 [get_ports UART_0_txd]
set_property PACKAGE_PIN L13 [get_ports UART_0_rxd]
set_property IOSTANDARD LVCMOS33 [get_ports UART_0_*] |
Code Block |
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language | ruby |
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title | _i_io.xdc |
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|
#RGB LED
#R
set_property PACKAGE_PIN J15 [get_ports {RGB_LED[0]}]
#G
set_property PACKAGE_PIN L14 [get_ports {RGB_LED[1]}]
#B
set_property PACKAGE_PIN K12 [get_ports {RGB_LED[2]}]
set_property IOSTANDARD LVCMOS33 [get_ports {RGB_LED[*]}]
|
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 2019.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2019.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_fsblTE modified 2019.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 2019.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin. |
Source location: \sw_lib\sw_apps
zynq_fsbl
TE modified 20192023.2 FSBL
General:
zynq_fsbl_app
TE modified 20192023.2 FSBL
General:
Module Specific:
- Add Files: all TE Files start with te_*
- Example app for LED access over MIO and sensor access(only pcb revisions 01 and 02) over I2C
- RGB LED access via AXI GPIO
- SD Card access rwrite/read file
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation on main.c
Additional Software
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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No additional software is needed.
Appx. A: Change History and Legal Notices
Scroll Ignore |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_dch |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | 2*,*,3*,4* |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Date | Document Revision | Authors | Description |
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Page info |
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infoType | Modified | modified-date | modified- date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| Page info |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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| Page info |
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infoType | Modified by |
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type | Flat |
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| | 2025-03-25 | | | | 2023-02-14 | v.9 | Waldemar Hanemann
| | 2020-04-16 | v.8 | John Hartfiel | | 2020-04-16 | v.7 | John Hartfiel | - separate template for FSBL with App included
| 2019-05-14 | v.6 | John Hartfiel | | 2018-08-15 | v.5 | John Hartfiel | | -- | all | Page info |
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infoType | Modified users |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| -- |
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Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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