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This chapter guides through the tasks which have to be done inside the Intel SoC Embedded Development Suite. As mentioned in page "Board bring-up overview for TEI0022" this step is for preloader and bootloader generation which should be done in the following three sections:

• Preparation
• Preloader/Bootloader generation
• Device Tree generation

The section "Preparation" describes preparing steps which are necessary for the generation of the preloader and the bootloader which is described in section "Preloader/Bootloader generation". After that in section "Device Tree generation" the steps to create the device tree blob is explained.

Preparation

While Intel Quartus Prime project compilation, described on page Intel Quartus Prime Project, folder "hps_isw_handoff" is created which is now needed to generate via the bsp-editor further output for preloader and bootloader generation. To do the preparation, follow the following guide:

Requirements - EIGENTLICH ÜBERFLÜSSIG, da auf Seite 0 geschrieben... . ?!?

All steps to format / setup a bootable SD card can only be performed within a Linux,
(Windows Subsystem for Linux is not capable to format a SD card) the Linux tool fdisk / sfdisk depend on it.

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Background

The boot process of the HPS consists of several stages:

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DIE GRAFIK GEHÖRT INTEL; DARF DIE HIER ÜBERHAUPT SEIN?---------------------------------------------------------

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The steps

BSP Editor

The BSP-Editor takes the handoff folder and generates further source and configuration files to be able to compile
the U-Boot Preloader and U-Boot Bootloader for the HPS.

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• Start the SoC EDS Shell as administrator. To do that navigate to

• C:\intelFPGA\18.1\embedded\

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• , right click on the file "Embedded_Command_Shell.

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• bat", and select "Run as administrator

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• ". Click Yes in the

...

• window

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• "User Account Control".

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• In the opened shell start the bsp-editor, as visible in the next figure, via: bsp-editor.exe

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Image Added

• In the opened bsp-editor select File → New HPS BSP...

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• In the opened New BSP

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• dialogue click onto

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• ... and select the PlatformEditorHPS_hps_0 folder inside

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• the hps_isw_handoff folder

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Back in the BSP-Editor, the U-Boot preloader must be configured. In the right column, under spl.boot are four Checkboxes,
each beginning with BOOT_FROM_... check only BOOT_FROM_SDMMC , the following three lines are of no interest.

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Image Added

• After that, click Open in this dialogue and OK in the previous dialogue.
• Now, in the bsp-editor, the preloader should be configured. Select only BOOT_FROM_SDMMC as BOOT_FROM_-parameter in the right window under the spl.boot header.
• Select FAT_SUPPORT.
• Select 1 as FAT_BOOT_PARTITION.
• Select u-boot.img as FAT_LOAD_PAYLOAD_NAME

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• .

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• Then, generate the output via clicking the Generate button.

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• After generation, an information like Finished generation BSP files. Total time taken =

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In your project folder, the folder - software - appears.

Image Removed Image Removed

U-Boot - Make preloader and main bootloader

The handoff folder contains now after the previous steps all the sources to compile the booot loaders.

On Windows 10 - Version 1909 - and cygwin - Version 2.0 - all commands which require decompressing of source archives, have to be
pointed into the right folder to be executed from, these commands beginn with    /usr/bin/ . All commands are in italic and bold,
comments to commands are in brackets.

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• ... seconds is displayed in the information tab. The folder software in the project path should now be available.
• Close the bsp-editor.

Preloader/Bootloader generation

After this preparation, it is possible to generate the preloader and the bootloader inside the shell while following the guide:

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• Change into folder .../software/spl_bsp inside the project folder with the change directory command cd. For example:

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• cd Project/software/spl_bsp

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• Clean the folder via running /usr/bin/make clean

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• Configure the build process via

• /usr/bin/make

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• config which generates

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• the folder .../software/spl_bsp

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• /uboot-socfpga.
• Generate the preloader via /usr/bin/make which generates the file .../software/spl_bsp/

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• preloader-mkpimage.bin

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• .

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• Generate the bootloader via /usr/bin/

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• make uboot which generates the image .../software/spl_bsp/uboot-socfpga/u-boot.img.
• If the make process ends with an error, try to rerun /usr/bin/make uboot until there is no error and the output is generated.

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 After that, the folder .../software/spl_bsp/ should look like the following figure.

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The folder .../software)To generate the main U-Boot boot loader, type:
    make uboot                  (Places the image u-boot.img into softwae/spl_bsp/uboot-socfpga )Image Removed Image Removedshould contain the files shown in the next figure.

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Device Tree

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Lastly, the Device Tree Blob must be generated, whereby Linux can start automated without user interaction.

It acts as an Interface from the board hardware to the Linux Kernel. The .dtb file informs the Linux Kernel about the existing Hardware,
its Configuration and which driver to use for controlling it.

Generate   - .dtb or .dts file from .sopcinfo file

C:\intelFPGA\18.1\embedded\examples\hardware\cv_soc_devkit_ghrd\tgz\soc_system_18_1_09132018_94307.tar.gz

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generation

The device tree generation is a crucial part to tell the linux kernel which hardware has to be handled. To generate the device tree blob follow this guide:

• For device tree generation the Golden Hardware Reference Design file .../intelFPGA/18.1/embedded/examples/hardware/cv_soc_devkit_ghrd/

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• hps_

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• common_

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• board_info.xml is needed. Therefore, copy this file into the project folder where the software folder, the output_files folder, ... are. This file contains information regarding the board which can be adapted, if necessary.
• Generate the device tree via the shell command: sopc2dts --input <Project Name>.sopcinfo --output socfpga

cd c:/temp/Project/ghrd_cyc5

tar xvf soc_system_18_1_09132018_94307.tar.gz

Das Programm "Device Tree Generator" / sopc2dts erzeugt ihn.

Unter "C:\intelFPGA\18.1\embedded\examples\hardware" findet sich das ghrd / Golden hardware standard
nach z.b.
driveLetter/PathToFolder/cv_soc_devkit_ghrd
entpacken
Aus dem Projekt nach nutzung des "Platform designers" , die erzeugt ....sopinfo in den Ordner kopieren.

Soc EDS Shell öffnen [Normal user is sufficient]
cd driveLetter:
cd driveLetter/PathToFolder/cv_soc_devkit_ghrd

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• .dtb --type dtb --board hps_common_board_info.xml --bridge-removal all --clocks

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• The output in the following listing can be ignored.

$ sopc2dts.exe --input PlatformEditorHPS.sopcinfo --output DTBsocfpga.dts --type dts --board hps_common_board_info.xml --bridge-removal all --clocks

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dts anstatt dtb erzeugen:
$ sopc2dts -i HPS.sopcinfo -o DTBsocfpga.dts -t dts --board hps_common_board_info.xml --bridge-removal all --clocks

Decompile - .dtb file to .dts file

C:\intelFPGA\18.1\embedded\host_tools\gnu\dtc\   dtc.exe

cd /cygdrive/c/intelFPGA/18.1/embedded/host_tools/gnu/dtc

dtc -I dts -O dtb -o device-tree.dtb devicetree.dts

Generate   - .dts file to .dtb file

cd /cygdrive/c/intelFPGA/18.1/embedded/host_tools/gnu/dtc

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MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null
MasterIF sopc2dts.lib.components.Interface@76fb509a slaveIF null
DTAppend: Unable to find parent, null, for #address-cells. Adding to root
DTAppend: Unable to find parent, null, for #size-cells. Adding to root
DTAppend: Unable to find parent, null, for reg. Adding to root
DTAppend: Unable to find parent, null, for spi-max-frequency. Adding to root
DTAppend: Unable to find parent, null, for m25p,fast-read. Adding to root
DTAppend: Unable to find parent, null, for page-size. Adding to root
DTAppend: Unable to find parent, null, for block-size. Adding to root
DTAppend: Unable to find parent, null, for tshsl-ns. Adding to root
DTAppend: Unable to find parent, null, for tsd2d-ns. Adding to root
DTAppend: Unable to find parent, null, for tchsh-ns. Adding to root
DTAppend: Unable to find parent, null, for tslch-ns. Adding to root
DTAppend: Unable to find parent, null, for cdns,page-size. Adding to root
DTAppend: Unable to find parent, null, for cdns,block-size. Adding to root
DTAppend: Unable to find parent, null, for cdns,read-delay. Adding to root
DTAppend: Unable to find parent, null, for cdns,tshsl-ns. Adding to root
DTAppend: Unable to find parent, null, for cdns,tsd2d-ns. Adding to root
DTAppend: Unable to find parent, null, for cdns,tchsh-ns. Adding to root
DTAppend: Unable to find parent, null, for cdns,tslch-ns. Adding to root