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Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

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All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

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• Xilinx
XA7Z020
• XC7Z020-1CLG484Q (Automotive)
• Rugged for shock and high vibration
• Dimensions: 6 x 6 cm
Temperature range: Automotive
• [XA7Z014S is available on other assembly options]
  • Package: CL/CLG484
  • Speed Grade: -1
  • Temperature Grade: Expanded (-40 to +128 °C)
• • 
    
• Dual-Core ARM Cortex-A9 MPCore
  
• 2 x 100 MBit Ethernet transceiver (PHY)
• 512 MByte DDR3L SDRAM, 16-bit-wide 
• DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
16 MByte
• QSPI Flash memory (with XiP support)
• Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
• [different size is available on other assembly options]
• Programmable SIT8918A , PS clock generator
• 2 Kbit serial EEPROM
• Three user LEDs
• CAN transceiver (PHY)
• 12 V power supply with watchdog
• On-board high-efficiency DC-DC converters
• System management and power sequencing
eFUSE bit-stream encryption
• AES bit-stream encryption
• Temperature compensated RTC (real-time clock)
• Three user LEDs
Evenly-spread supply pins for good signal integrity
Other assembly options for cost or performance optimization plus high volume prices available on request.

Depending on the customer design, additional cooling might be required.

Block Diagram

• 2 x 100 MBit Ethernet transceiver (PHY)
• Board to Board (B2B)
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
• I/O Interface
  • 42x MIO
  • 200x HR
  • 128x PS IO
  • 0x GTP Transceiver
  • 0x GTX Transceiver

• Power Supply
  • 12 V power supply with watchdog
• Others:
  • Dimensions: 6 x 6 cm
  • Rugged for shock and high vibration
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
  • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Evenly-spread supply pins for good signal integrity
    
    

Block Diagram

Main Components

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1. DDR3 SDRAM, U1
2. 512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
3. Xilinx Automotive XA7Z020-1CLG484Q ,U2
4. 100 MBit Ethernet transceiver  DP83848transceiver, U3
5. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
6. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
7. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
8. Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
10. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
11. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
12. 64 Kbit I2C EEPROM, 24LC64, U11
13. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
14. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
15. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
16. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
17. CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
18. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM2
19. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM3
20. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
    

Initial Delivery State

1. 100 MBit Ethernet transceiver, U10
2. User LED Green, D4
3. Real Time Clock, U7
4. Standard Clock Oscillators, U5
5. 64 Kbit I2C EEPROM, U11
6. CAN Tranceiver, U16
7. QSPI NOR Flash memory, U13
8. Standard Clock Oscillators, U14
9. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
10. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
11. B2B connector , JM2
12. B2B connector , JM3
13. B2B connector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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Configuration Signals

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Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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Signals, Interfaces and Pins

Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:JTAG InterfaceJTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.

On-board Peripherals