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Table of Contents
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Overview
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Refer to "https://shop.trenz-electronic.de/en/Download/?path=Trenz_Electronic/TE0803" for downloadable version of this manual and the rest of available documentation. |
The Trenz Electronic TE0803 is an industrial-grade MPSoC SoM integrating a Xilinx Zynq UltraScale+, max. 8 GByte DDR4 SDRAM with 64-Bit width data bus connection, max. 512 MByte SPI Boot Flash memory for configuration and operation, up to 8 Gigabit transceivers and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections.
All this in a compact 5.2 x 7.6 cm form factor, at the most competitive price.
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Key Features
- Xilinx Zynq UltraScale+ MPSoC 784 pin package (options: ZU2CG, ZU2EG, ZU3CG, ZU3EG, ZU4CG, ZU4EV)
- Memory
- 64-Bit DDR4, 8 GByte maximum
- Dual SPI boot Flash in parallel, 512 128 MByte maximum - User I/O
- 65 x MIO, 48 x HD (all), 156 x HP (3 banks)
- Serial transceiver: 4 x GTR (+ 4 x GTH transceiver with ZU4CG or ZU4EV MPSoC)
- Transceiver clocks inputs and outputs
- PLL clock generator inputs and outputs - Size: 52 x 76 mm, 3 mm mounting holes for skyline heat spreader
- B2B connectors: 4 x 160 pin
- Si5338A - 4 output PLL
- All power supplies on board, single 3.3V power source required
- LP, FP, PL separately controlled power domains - Support for all boot modes (except NAND) and scenarios
- Support for any combination of PS connected peripherals
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- Xilinx ZYNQ UltraScale+ MPSoC, U1
- 2-Input AND Gate, U39
- Red LED (DONE), D1
- 256Mx16 DDR4-2400 SDRAM, U12
- 256Mx16 DDR4-2400 SDRAM, U9
- 256Mx16 DDR4-2400 SDRAM, U2
- 256Mx16 DDR4-2400 SDRAM, U3
- 12A PowerSoC DC-DC converter, U4 (either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)
- 1.5A LDO DC-DC converter, U10
- 1.5A LDO DC-DC converter, U8
- Voltage monitor circuit, U41
- 0.35A LDO DC-DC converter, U26
- 0.35A LDO DC-DC converter, U27
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J3
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J1
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J4
- Ultra fine 0.50 mm pitch, Razor Beam™ LP Slim Terminal Strip with 160 contacts, J2
- 4-channel programmable PLL clock generator, U5
- Low-power programmable oscillator @ 25.000000 MHz, U5
- Low-power programmable oscillator @ 33.333333 MHz (PS_CLK), U32
- 256 Mbit serial NOR Flash memory, U7
- 256 Mbit serial NOR Flash memory, U17
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Storage device name | Content | Notes |
---|---|---|
User configuration EEPROMs with MAC address (1x Microchip 24LC128-I/ST, 3x Microchip 24AA025E48T-I/OT) | Not programmed | available since PCB REV02 |
SPI Flash main array | Not programmed | - |
eFUSE Security | Not programmed | - |
Si5338A programmable PLL NVM OTP | Not programmed- | Only volatile memory is programmable of field. NVM can't be program on field. Custom assembly variant with preprogrammed NVM is possible on request |
Table 1: Initial Delivery State of the flash memories
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Bank | Type | B2B Connector | Schematic Names / Connector Pins | I/O Signal Count | LVDS Pairs Count | VCCO Bank Voltage | Notes | |||
---|---|---|---|---|---|---|---|---|---|---|
251) | HD | J3 | B25_L1_P ... B25_L12_P | 24 I/O's | 12 | VCCO25 | VCCO max. 3.3V | |||
262) | HD | J3 | B26_L1_P ... B26_L12_P | 24 I/O's | 12 | VCCO26 | VCCO max. 3.3V | |||
64 | HP | J4 | B64_L1_P ... B64_L24_P B64_T0 ... B64_T3 | 52 48 I/O's | 24 | VCCO64 | VCCO max. 1.8V | |||
6465 | HP | J4 | B65_L1_P ... B65_L24_P B65B_64_T0 ... BB65_64_T3 | 52 I/O's | 24 | VCCO65 | 4 I/O's | - | VCCO64 | VCCO max. 1.8V usable as single-ended I/O's |
6566 | HP | J4J1 | B65B66_L1_P ... B65B66_L24_P B66_T0 ... B66_T3 | 52 48 I/O's | 24 | VCCO66VCCO65 | VCCO max. 1.8V | |||
65500 | HPMIO | J4 | J3 | MIO13 B_65_T0 ... B_65_T3 pins J4-7, J4-5, J4-3, J4-1MIO25 | 13 I4 I/O's | - | VCCO65 | PS_1V8 | user configurable VCCO max. 1.8V only single-ended I/O's on B2B | |
66501 | HPMIO | J1 | J3 | MIO26 B66_L1_P ... B66_L24_P B66_L1_N ... B66_L24_NMIO51 | 26 48 I/O's | 24- | VCCO66 | PS_1V8 | user configurable VCCO max. 1.8V usable as single-ended I/O's on B2B | |
66502 | HPMIO | J1 | J3 | MIO52 B_65_T0 ... B_65_T3 pins J1-147, J1-145, J1-143, J1-141MIO77 | 26 4 I/O's | - | VCCO66 | PS_1V8 | user configurable VCCO max. 1.8V only single-ended I/O's | |
500 | MIO | J3 | MIO13 ... MIO25 | 13 I/O's | - | PS_1V8 | user configurable I/O's on B2B | |||
501 | MIO | J3 | MIO26 ... MIO51 | 26 I/O's | - | PS_1V8 | user configurable I/O's on B2B | |||
502 | MIO | J3 | MIO52 ... MIO77 | 26 I/O's | - | PS_1V8 | user configurable I/O's on B2B |
Table 2: B2B connector pin-outs of available PL and PS banks of the TE0803-01 SoM
1) Bank 25 at XCZU2 / XCZU3, else Bank 45 at XCZU4 / XCZU5
2) Bank 26 at XCZU2 / XCZU3, else Bank 46 at XCZU4 / XCZU5
All MIO banks are powered from on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.
For detailed information about the B2B pin-out, please refer to the Pin-out table.
The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.
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on B2B |
Table 2: B2B connector pin-outs of available PL and PS banks of the TE0803-01 SoM
1) Bank 25 at XCZU2 / XCZU3, else Bank 45 at XCZU4 / XCZU5
2) Bank 26 at XCZU2 / XCZU3, else Bank 46 at XCZU4 / XCZU5
All MIO banks are powered from on-module DC-DC power rail. All PL I/O banks have separate VCCO input pins in the B2B connectors, valid VCCO should be supplied from the carrier board.
For detailed information about the B2B pin-out, please refer to the Pin-out table.
The configuration of the I/O's MIO13 - MIO77 are depending on the base-board peripherals connected to these pins.
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MGT Lanes
The B2B connectors J1 and J2 provide also access to the MGT banks of the Zynq UltraScale+ MPSoC. There are 8 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).
The MGT banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT lanes are available on the B2B connectors:
Bank | Type | B2B Connector | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs |
---|---|---|---|---|---|
2241) | GTH | J1 | 4 GTH lanes (4 RX / 4TX) | B224_RX3_P, B224_RX3_N, pins J1-51, J1- |
MGT Lanes
The B2B connectors J1 and J2 provide also access to the MGT banks of the Zynq UltraScale+ MPSoC. There are 8 high-speed data lanes (Xilinx GTH / GTR transceiver) available composed as differential signaling pairs for both directions (RX/TX).
The MGT banks have also clock input-pins which are exposed to the B2B connectors J2 and J3. Following MGT lanes are available on the B2B connectors:
Bank | Type | B2B Connector | Count of MGT Lanes | Schematic Names / Connector Pins | MGT Bank's Reference Clock Inputs |
---|---|---|---|---|---|
2241)
| GTH | J1 | 4 GTH lanes | B224_RX3_P, B224_RX3_N, pins J1-51, J1-53 B224_RX2_P, B224_RX2_N, pins J1-57, J1-59 B224_RX1_P, B224_RX1_N, pins J1-63, J1-65 B224_RX0_P, B224_RX0_N, pins J1-69, J1-71 | 1 reference clock signal (B224_CLK0) from B2B connector 1 reference clock signal (B224_CLK1) from programmable |
505 | GTR | J2 | 4 GTR lanes (4 RX / 4TX) | B505_RX3_P, B505_RX3_N, pins J2-5154, J2-4952 B505_RX2_P, B505_RX2_N, pins J2-5760, J2-5558 B505_RX1_P, B505_RX1_N, pins J2-6366, J2-6164 B505_RX0_P, B505_RX0_N, pins J2-6972, J2-6770 | 2 reference clock signals (B505_CLK0, B505_CLK1) from B2B connector 2 reference clock signals (B505_CLK2, B505_CLK3) from programmable |
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1) Bank 224 only available at ZU4CG or ZU4EV at XCZU4 / XCZU5 MPSoC.
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JTAG Interface
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Signal | B2B Connector Pin | Function |
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DONE | J2-116 | PL configuration completed |
PROG_B | J2-100 | PL configuration reset signal |
INIT_B | J2-98 | PS is initialized after a power-on reset |
SRST_B | J2-96 | System reset |
MODE0 ... MODE3 | J2-109/J2-107/J2-105/J2-103 | 4-bit boot mode pins For further information about the boot-modes refer to the Xilinx Zynq UltraScale+ MPSoC TRM |
ERR_STATUS / ERR_OUT | J2-86 / J2-88 | ERR_OUT signal is asserted for accidental loss of ERR_STATUS indicates a secure lockdown lock-down state |
PUDC_B | J2-127 | Pull-up during configuration (pulled-up to 'PL_1V8') |
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Quad SPI Flash memory ICs U7 and U17 are connected to the Zynq PS QSPI0 interface via PS MIO bank 500, pins MIO0..MIO5 and MIO7..MIO12.
MIO | U7 Pin | Pin Name | MIO | U17 Pin | Pin Name | ||
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0 | B2 | CLK | 7 | C2 | CS# | ||
1 | D2 | DO/IO1 | 8 | D3 | DI/IO0 | ||
2 | C4 | WP#/IO2 | 9 | D2 | DO/IO1 | ||
3 | D4 | HOLD#/IO3 | 10 | C4 | WP#/IO2 | ||
4 | D3 | DI/IO0 | 11 | D4 | HOLD#/IO3 | ||
5 | C2 | CS# | 12 | B2 | CLK |
Table 7: MIO pin assignment of the Quad SPI Flash memory ICs
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Following boot modes are possible on the TE0803 UltraScale+ MPSoC module by generating the corresponding 4-bit code with pins 'PS_MODE0' ... 'PS_MODE3' (little-endian alignment):
Boot Mode | Mode Pins [3:0] | MIO Location | Description |
---|---|---|---|
JTAG | 0x0 | JTAG | Dedicated PS interface. |
QSPI32 | 0x2 | MIO[12:0] | Configured on module with dual QSPI Flash Memory. 32-bit addressing. |
configurations. |
supported. | |||
SD0 | 0x3 | MIO[25:13] | Supports SD 2.0. |
SD1 | 0x5 | MIO[51:38] | Supports SD 2.0. |
eMMC_18 | 0x6 | MIO[22:13] | Supports eMMC 4.5 at 1.8V. |
USB 0 | 0x7 | MIO[52:63] | Supports USB 2.0 and USB 3.0. |
PJTAG_0 | 0x8 | MIO[29:26] | PS JTAG connection 0 option. |
SD1-LS | 0xE | MIO[51:39] | Supports SD 3.0 with a required |
Table 9: Selectable boot modes by dedicated boot mode pins
For Functional functional details see see ug1085 - Zynq UltraScale+ TRM (Boot Modes Section).
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The TE0803 SoM can be configured with max. 512 MByte Flash Memory memory for configuration and operation. Flash size and type depends on assembly version.
Name | IC | Designator | PS7 | MIO | Notes |
---|---|---|---|---|---|
SPI Flash | N25Q256A11E1240E | U7 | QSPI0 | MIO0 ... MIO5 | Dual parallel booting possible, 32 MByte memory per Flash IC at standard configuration |
SPI Flash | N25Q256A11E1240E | U17 | QSPI0 | MIO7 ... MIO12 | As above |
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The TE0803-01 SoM is equipped with with four DDR4-2400 SDRAM modules chips with up to 8 GByte of memory density. The SDRAM modules chips are connected to the Zynq MPSoC's PS DDR controller (bank 504) with a via 64-bit wide data bus width.
Refer to the Xilinx Zynq UltraScale+ data sheet DS925 to get datasheet DS925 for more information, if the specific package of the Zynq UltraScale+ MPSoC equipped chip on module supports the maximum data transmission rate of 2400 MByte/s.
Configuration EEPROM
The TE0803 (PCB REV02 or newer) contains EEPROMs for general user purposes and mac address. The EEPROMs are provided by Microchip and all have I²C interfaces:
EEPROM Modell | Schematic Designator | Memory Density | Purpose |
---|---|---|---|
24AA025E48T-I/OT | U41 | 2 Kbit | user |
Table 21: On-board configuration EEPROMs overview
Programmable PLL Clock Generator
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Input | Connected to | Frequency | Notes |
---|---|---|---|
IN1 / IN2 | B2B Connector pins J2-4, J2-6 (differential pair) | User | AC decoupling required on base |
IN3 | On-board Oscillator (U6) | 25.000000 MHz | - |
Output | Connected to | Frequency | Notes |
CLK0 A/B | B2B Connector pins J2-1, J2-3 (differential pair) | User | Default off |
CLK1 A/B | B224 CLK1 (only available at ZU5EV MPSoC )with ZU4 and higher ) | User | Default off |
CLK2 A/B | B505 CLK3 | User | Default off |
CLK3 A/B | B505 CLK2 | User | Default off |
Table 11: Programmable PLL clock generator input/output
The Si5345A Si5338A programmable clock generator's control interface pins are exposed to B2B connector J2. For further information refer to the Si5338A data sheet.
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Table 12: B2B connector pin-out of Si5338A control interface
Note |
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Si5338A OTP ROM Si5338A NVM is not programmed by default at delivery, so it . It is customers responsibility to either configure Si5338A volatile memory during FSBL or then use Silicon Labs programmer and burn the OTP ROM with customer fixed clock setup. |
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. Custom assembly variant with preprogrammed NVM is possible on request. |
Refer to Si5338A datasheet for more information.
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Figure 3: Power Distribution Diagram (For U4 either TPS548A28RWWR or MPQ8633BGLE-Z is assembled which is up to Trenz Electronic GmbH)
Note |
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Current rating of Samtec Razor Beam™ LSHM B2B Beam LP Terminal/Socket Strip ST5/SS5 B2B connectors is 21.0A 5 A per pin (2 adjacent pins powered1 pin powered per row). |
Power-On Sequence Diagram
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The control signals have to be asserted on the B2B connector J2, whereby some of the Power - Good - Signals need external pull-up resistors.
Enable-Signal | B2B Connector Pin | Max. Voltage | Note | Power-Good-Signal | B2B Connector Pin | Pull-up Resistor | Note | ||
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EN_LPD | J2-108 | 6V | TPS82085SIL data sheet | LP_GOOD | J2-106 | 4K7, pulled up to LP_DCDC | - | ||
EN_FPD | J2-102 | DCDCIN | NC7S08P5X data sheet | PG_FPD | J2-110 | 4K7, pulled up to DCDCIN | - | ||
EN_PL | J2-101 | max PL_DCIN | Left floating for logic high (drive to GND for logic low) | PG_PL | J2-104 | External pull-up needed (max. voltage 'GT_DCDC'), Max. sink current 1 mA | TPS82085SIL / | ||
EN_DDR | J2-112 | DCDCIN | NC7S08P5X data sheet | PG_DDR | J2-114 | 4K7, pulled up to DCDCIN | - | ||
EN_PSGT | J2-84 | DCDCIN | NC7S08P5X data sheet | PG_PSGT | J2-82 | External pull-up needed (max. 5.5V), Max. sink current 1 mA | TPS74801 datasheet | ||
EN_GT_R | J2-95 | GT_DCDC | NC7S08P5X data sheet | PG_GT_R | J2-91 | External pull-up needed (max. 5.5V), Max. sink current 1 mA | TPS74401 datasheet | ||
- | - | - | - | PG_VCU_1V0 | J2-97 | External pull-up needed (max. 5.5V), | TPS82085SIL datasheet |
Table 16: Recommended operation conditions of DC-DC converter control signals
Warning |
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To avoid any damage to the MPSoC module, check for stabilized on-board voltages in steady state before powering up the MPSoC's I/O bank voltages VCCOx. All I/O's should be tri-stated during power-on sequence. |
Core voltages and main supply voltages have to reach stable state and their "Power Good" - signals have to be asserted before other voltages like bank 's I/O voltages (VCCOx) can be powered up.
It is important that all PS and PL I/Os are tri-stated at power-on until the "Power Good" - signals are high, meaning that all on-module voltages have become stable and module is properly powered up.
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The voltages 'LP_DCDC' and 'LP_0V85' are monitored by the voltage monitor circuit U41, which generates the POR_B reset signal at Power-On. A manual reset is also possible by driving the MR-pin (J2-83) to GND. Leave this pin unconnected or connect to VDD (LP_DCDC) when unused.
Figure 5: Voltage monitor circuit
Power Rails
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Table 17: Power rails of the MPSoC module on accessible connectors
Bank Voltages
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Table 18: Range of MPSoC module's bank voltages
B2B connectors
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Variants Currently In Production
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Figure 5: Voltage monitor circuit
Power Rails
Voltages on B2B Connectors | B2B J1 Pin | B2B J2 Pin | B2B J3 Pin | B2B J4 Pin | Input/ Output | Note |
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PL_DCIN | J1-151, J1-153,J1-155, J1-157, J1-159 | - | - | - | Input | - |
DCDCIN | - | J2-154, J2-156, J2-158, J2-160, J2-153, J2-155, J2-157, J2-159 | - | - | Input | - |
LP_DCDC | - | J2-138, J2-140, J2-142, J2-144 | - | - | Input | - |
PS_BATT | - | J2-125 | - | - | Input | - |
GT_DCDC | - | - | J3-157, J3-158, J3-159, J3-160 | - | Input | - |
PS_1V8 | - | J2-99 | J3-147, J3-148 | - | Output | Internal voltage level 1.8V nominal output |
PL_1V8 | J1-91, J1-121 | - | - | - | Output | Internal voltage level 1.8V nominal output |
DDR_1V2 | - | J2-135 | - | - | Output | Internal voltage level 1.2V nominal output |
Table 17: Power rails of the MPSoC module on accessible connectors
Bank Voltages
Bank | Type | Schematic Name / B2B Connector Pins | Voltage | Reference Input Voltage | Voltage Range |
---|---|---|---|---|---|
25 | HD | VCCO25, pins J3-15, J3-16 | User | - | Max. 3.3V |
26 | HD | VCCO26, pins J3-43, J3-44 | User | - | Max. 3.3V |
64 | HP | VCCO64, J4-58, J4-106 | User | VREF_64, pin J4-88 | Max. 1.8V |
65 | HP | VCCO65, J4-69, J4-105 | User | VREF_65, pin J4-15 | Max. 1.8V |
66 | HP | VCCO66, J1-90, J1-120 | User | VREF_66, pin J1-108 | Max. 1.8V |
500 | MIO | PS_1V8 | 1.8V | - | - |
501 | MIO | PS_1V8 | 1.8V | - | - |
502 | MIO | PS_1V8 | 1.8V | - | - |
503 | CONFIG | PS_1V8 | 1.8V | - | - |
Table 18: Range of MPSoC module's bank voltages
B2B connectors
Include Page | ||||
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Variants Currently In Production
Trenz shop TE0803 overview page | |
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English page | German page |
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Unit | Notes / Reference Document |
---|---|---|---|---|
PL_DCIN | -0.3 | 4 | V | TPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG |
DCDCIN | -0.3 | 4 | V | TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG |
LP_DCDC | -0.3 | 4 | V | TPS3106K33DBVR data sheet |
GT_DCDC | -0.3 | 4 | V | TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG |
PS_BATT | -0.5 | 2 | V | Xilinx DS925 data sheet |
VCCO for HD I/O banks | -0.5 | 3.4 | V | Xilinx DS925 data sheet |
VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet |
VREF | -0.5 | 2 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
I/O input voltage for HP I/O banks | -0.55 | VCCO + 0.55 | V | Xilinx DS925 data sheet |
PS I/O input voltage (MIO pins) | -0.5 | VCCO_PSIO + 0.55 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally |
Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.5 | 1.2 | V | Xilinx DS925 data sheet |
Voltage on input pins of NC7S08P5X 2-Input AND Gate | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC |
Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41 | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, VDD = LP_DCDC |
"Enable"-signals on TPS82085SIL ('EN_LPD') | -0.3 | 7 | V | TPS82085SIL data sheet |
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
Note |
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Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
Table 19: Differences between module TE0803-01 variants
1) Not yet available
All variants are rated for Extended temperature range (0 - 100 °C).
Technical Specifications
Absolute Maximum Ratings
Parameter | Min | Max | Unit | Notes / Reference Document | |||||||
---|---|---|---|---|---|---|---|---|---|---|---|
PL_DCIN | -03.3 | 73.6 | V | EN63A0QI / TPS82085SIL / EN63A0QI data sheet / Limit is LP_DCDC over EN/PG | |||||||
DCDCIN | -03.3 | 73.6 | V | TPS82085SIL / TPS51206PSQ data sheet / Limit is LP_DCDC over EN/PG | |||||||
LP_DCDC | -03.3 | 43.6 | V | TPS3106K33DBVR data sheet | |||||||
GT_DCDC | -03.3 | 73.6 | V | TPS82085SIL data sheet / Limit is LP_DCDC over EN/PG | |||||||
PS_BATT | 1.2 | 1-0.52 | V | Xilinx DS925 data sheet | |||||||
VCCO for HD I/O banks | -01.514 | 3.4 | V | Xilinx DS925 data sheet | |||||||
VCCO for HP I/O banks | -0.5 | 2 | V | Xilinx DS925 data sheet | VREF | -0.5 | 2 | 95 | 1.9 | V | Xilinx DS925 data sheet |
I/O input voltage for HD I/O banks. | -0.552 | VCCO + 0.552 | V | Xilinx DS925 data sheet | |||||||
I/O input voltage for HP I/O banks | -0.552 | VCCO + 0.552 | V | Xilinx DS925 data sheet | |||||||
PS I/O input voltage (MIO pins) | -0.52 | VCCO_PSIO + 0.552 | V | Xilinx DS925 data sheet, VCCO_PSIO 1.8V nominally | |||||||
Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage | -0.5 | 1.2 | V | Xilinx DS925 data sheet | |||||||
Voltage on input pins of NC7S08P5X 2-Input AND Gate | 0 | VCC | V | NC7S08P5X data sheet, see schematic for connected VCCs | |||||||
Voltage on input pins (MR) of NC7S08P5X 2-Input AND Gate | -0.5 | VCC + 0.5 | V | NC7S08P5X data sheet, see schematic for VCC | |||||||
Voltage on input pins (nMR) of TPS3106K33DBVR Voltage Monitor, U41 | -0.3 | VDD + 0.3 | V | TPS3106 data sheet, VDD = LP_DCDC | |||||||
"Enable"-signals on TPS82085SIL ('EN_LPD') | -0.3 | 7 | V | TPS82085SIL data sheet | |||||||
Storage temperature (ambient) | -40 | 100 | °C | ROHM Semiconductor SML-P11 Series data sheet |
Note |
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Assembly variants for higher storage temperature range are available on request. |
Recommended Operating Conditions
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TPS3106K33DBVR Voltage Monitor, U41 | 0 | VDD | V | TPS3106 data sheet, VDD = LP_DCDC |
Note |
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Please check Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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Physical Dimensions
- Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
- Mating height with standard connectors: 5mm
- PCB thickness: 1.6mm
- Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Revision History
Hardware Revision History
Date | Revision | Notes | Link to PCN | Documentation Link |
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2019-03-18 | 03 |
| TE0803 Product Change Notifications | TE0803-03 |
2018-07-19 | 02 |
| TE0803 Product Change Notifications | TE0803-02 |
2016-12-23 | 01 | First production release | - | TE0803-01 |
Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Document Change History
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22-02-25 | v.50 | John Hartfiel |
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22-02-08 | v.46 | John Hartfiel |
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2021-05-17 | v.41 | John Hartfiel |
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2021-03-11 | v.40 | John Hartfiel |
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2019-07-15 | v.36 | John Hartfiel |
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2019-07-02 | v.35 | John Hartfiel |
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2019-06-19 | v.33 | John Hartfiel |
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2018-08-20 | v.29 | John Hartfiel |
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2018-08-06 | v.28 | John Hartfiel |
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2017-11-13 | v.23 | Ali Naseri |
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2017-11-13 | v.19 | John Hartfiel |
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2017-10-19 | v.18 | John Hartfiel |
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2017-08-15 | v.17 | Vitali Tsiukala |
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2017-08-07 | v.14 |
Note |
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Please check Xilinx datasheet DS925 for complete list of absolute maximum and recommended operating ratings. |
Operating Temperature Ranges
Extended grade: 0°C to +100°C.
The module operating temperature range depends also on customer design and cooling solution. Please contact us for options.
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Physical Dimensions
- Module size: 52 mm × 76 mm. Please download the assembly diagram for exact numbers
- Mating height with standard connectors: 4mm
- PCB thickness: 1.6mm
- Highest part on PCB: approx. 3mm. Please download the step model for exact numbers
All dimensions are given in millimeters.
Revision History
Hardware Revision History
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Hardware revision number is written on the PCB board together with the module model number separated by the dash.
Document Change History
Date | Revision | Contributors | Description |
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2017-08-06 | Jan Kumann |
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2017-05-17 | V.4 | Ali Naseri | Current TRM release. |
2017-05-10 | v.1 | Ali Naseri | Initial document. |
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