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Important General Note:
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Export PDF to download, if vivado revision is changed!
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Table of contents
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Overview
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Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.
Refer to http://trenz.org/te0745-info for the current online version of this manual and other available documentation.
Key Features
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Revision History
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title | Design Revision History |
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- 2019.2 update
- FSBL rework, SI5338 Project with Clock Builder pro
- device tree update
- Vitis support
- new assembly variants
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- BUGFIX in TE0745-02-45-3EA board parts
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TE0745-test_board-vivado_2018.2-build_03_20181126115131.zip
TE0745-test_board_noprebuilt-vivado_2018.2-build_03_20181126115320.zip
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- Rework Board Part Files
- New assembly versions
- Rework BD Design
- add init.sh scripts
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- initial release
Release Notes and Know Issues
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title | Known Issues |
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Requirements
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Hardware
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Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
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title | Hardware Modules |
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Design supports following carriers:
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Additional HW Requirements:
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title | Additional Hardware |
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Content
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For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
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Additional Sources
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title | Additional design sources |
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Prebuilt
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title | Prebuilt files |
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File
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File-Extension
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Description
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Debian SD-Image
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*.img
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Debian Image for SD-Card
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MCS-File
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*.mcs
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Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only)
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MMI-File
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*.mmi
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File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only)
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SREC-File
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*.srec
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Converted Software Application for MicroBlaze Processor Systems
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title | Prebuilt files (only on ZIP with prebult content) |
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File
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Description
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Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
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Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
- AMD Development Tools#XilinxSoftware-BasicUserGuides
- Vivado Projects - TE Reference Design
- Project Delivery.
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
- Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process)
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
Note: Select correct one, see TE Board Part Files
- (optional for manual changes) Select correct device and Xilinx install path on "design_basic_settings.cmd" and create Vivado project with "vivado_create_project_guimode.cmd"
- Create XSA and export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use GUI is the same, except file export to prebuilt folder
- Run on Vivado TCL: TE::hw_build_design -export_prebuilt
- Create Linux (uboot.elf and image.ub) with exported XSA
- XSA is exported to "prebuilt\hardware\<short name>"
Note: HW Export from Vivado GUI create another path as default workspace. - Create Linux images on VM, see PetaLinux KICKstart
- Use TE Template from /os/petalinux
- XSA is exported to "prebuilt\hardware\<short name>"
- Add Linux files (uboot.elf and image.ub) to prebuilt folder
- "prebuilt\os\petalinux\<ddr size>" or "prebuilt\os\petalinux\<short name>"
- Generate Programming Files with Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate applications and bootable files, which are defined in "sw_lib\apps_list.csv" - (alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TCL scripts generate also platform project, this must be done manuelly in case GUI is used. See Vitis
- Run on Vivado TCL: TE::sw_run_vitis -all
Launch
Programming
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Check Module and Carrier TRMs for proper HW configuration before you try any design. |
Xilinx documentation for programming and debugging: Vivado/SDK/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
- Select Create and open delivery binary folder
Note: Folder (<project foler>/_binaries_<Artikel Name>) with subfolder (boot_<app name>) for different applications will be generated
QSPI
Optional for Boot.bin on QSPI Flash and image.ub on SD.
- Connect JTAG and power on carrier with module
- Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
- Type on Vivado TCL Console: TE::pr_program_flash -swapp u-boot
Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
optional "TE::pr_program_flash -swapp hello_te0745" possible - Copy image.ub and init.sh (optional on /misc/sd) on SD-Card
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Insert SD-Card
SD
- Copy image.ub,Boot.bin and init.sh (optional on /misc/sd) on SD-Card.
- use files from (<project foler>/_binaries_<Articel Name>)/boot_linux from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see <design_name>/prebuilt/readme_file_location.txt
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
- Select SD Card as Boot Mode
Note: See TRM of the Carrier and Module. - Power On PCB
Note: 1. Zynq Boot ROM loads FSBL from SD into OCM, 2. FSBL loads U-boot from SD into DDR and program PL part, 3. U-boot load Linux from SD into DDR
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
- COM Port: Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1)
- Linux Console:
Note: Wait until Linux boot finished For Linux Login use:- User Name: root
- Password: root
- You can use Linux shell now.
- I2C 0 Bus type: i2cdetect -y -r 0
- RTC check: dmesg | grep rtc
- ETH0 works with udhcpc
- USB type "lsusb" or connect USB2.0 device
- (optional) init.sh scripts: Scripts will enable SFP interface after linux booting, if file is copied on SD
Vivado HW Manager
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Monitoring:
SI5338 CLKs:
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz, SI5338 CLK(0 and 3) are configured to 125MHz by default.
- Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder).Set radix from VIO signals to unsigned integer.
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System Design - Vivado
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Block Design
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*clk3 is not available on the smallest SOC (xc7z030) |
PS Interfaces
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Activated interfaces:
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Constrains
Basic module constrains
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design] |
Design specific constrain
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set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk0_clk_p]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk3_clk_p]
set_false_path -from [get_clocks si5338_clk0_clk_p] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks si5338_clk3_clk_p] -to [get_clocks clk_fpga_0] |
Software Design - Vitis
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For SDK project creation, follow instructions from:
Application
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FPGA Example
scu
MCS Firmware to configure SI5338 and Reset System.
srec_spi_bootloader
TE modified 2019.2 SREC
Bootloader to load app or second bootloader from flash into DDR
Descriptions:
- Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11
TE modified 2019.2 xilisf_v5_11
- Changed default Flash type to 5.
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Zynq Example:
zynq_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
ZynqMP Example:
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zynqmp_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c(search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
zynqmp_pmufw
Xilinx default PMU firmware.
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General Example:
hello_te0820
Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Template location: ./sw_lib/sw_apps/
zynq_fsbl
TE modified 2019.2 FSBL
General:
- Modified Files:main.c, fsbl_hooks.h/.c (search for 'TE Mod' on source code)
Add Files: te_fsbl_hooks.h/.c(for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device ID
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
zynq_fsbl_flash
TE modified 2019.2 FSBL
General:
- Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0745
Hello TE0745 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. SDK/HSI is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC=""
U-Boot
Start with petalinux-config -c u-boot
Changes:
- CONFIG_ENV_IS_NOWHERE=y
- # CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_I2C_EEPROM=y
- CONFIG_ZYNQ_GEM_I2C_MAC_OFFSET=0xFA
- CONFIG_SYS_I2C_EEPROM_ADDR=0x53
- CONFIG_SYS_I2C_EEPROM_BUS=0
- CONFIG_SYS_EEPROM_SIZE=256
- CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=0
- CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=0
- CONFIG_SYS_I2C_EEPROM_ADDR_LEN=1
- CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW=0
Change platform-top.h:
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Device Tree
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Kernel
Start with petalinux-config -c kernel
Changes:
- CONFIG_RTC_DRV_ISL12022=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- i2c-tools
- CONFIG_busybox-httpd=y (for web server app)
- CONFIG_packagegroup-petalinux-utils(util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
Applications
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application accemble for Zynq access. Need busybox-httpd
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