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<!-- tables have all same width (web max 1200px and pdfPDF full page(640px), flexible width or fix width on menu for single column can be used as before) -->
<style>
.wrapped{
  width: 100% !important;
  max-width: 1200px !important;
 }
</style>

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  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

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        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

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      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefaultstyle
        widthssortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

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        • main section:
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          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
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Table of Contents

Table of Contents

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Notes :

Trenz Electronic TE0728 is an automotive-grade FPGA module integrating a Xilinx Automotive an Automotive Xilinx  Zynq-7020 7 FPGA, two 100 Mbit Ethernet transceivers (PHY) , 512 MByte DDR3L SDRAM, 16 MByte DDR3 SDRAM, QSPI Flash memory for configuration and operation, and powerful switching-mode power supplies for all on-board voltages. Numerous configurable I/Os are provided via rugged high-speed strips. 

...

All this in a compact 6 x 6 cm form factor, at the most competitive price.

Refer to http://trenz.org/te0728-info for the current online version of this manual and other available documentation.

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    • Note:
  • Xilinx
    • XA7Z020
  • XC7Z020-1CLG484Q (Automotive)
  • Rugged for shock and high vibration
  • Dimensions: 6 x 6 cm
    • Temperature range: Automotive
  • [XA7Z014S is available on other assembly options]
    • Package: CL/CLG484
    • Speed Grade: -1
    • Temperature Grade: Expanded (-40 to +128 °C)

  • Dual-Core ARM Cortex-A9 MPCore
  • 2 x 100 MBit Ethernet transceiver (PHY)
  • 512 MByte DDR3L SDRAM, 16-bit-wide 
  • DDR3 SDRAM, up to 512MB, up to 1066 Mb/s, connected to PS  [different size is available on other assembly options]
    • 16 MByte
  • QSPI Flash memory (with XiP support)
  • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
    • 76 single ended I/O, 24 LVDS pairs (48 I/O) and 42 MIO available on board-to-board connectors
  • [different size is available on other assembly options]
  • Programmable SIT8918A , PS clock generator
  • 2 Kbit serial EEPROM
  • Three user LEDs
  • CAN transceiver (PHY)
  • 12 V power supply with watchdog
  • On-board high-efficiency DC-DC converters
  • System management and power sequencing
    • eFUSE bit-stream encryption
  • AES bit-stream encryption
  • Temperature compensated RTC (real-time clock)
  • Three user LEDs
    • Evenly-spread supply pins for good signal integrity
    Other assembly options for cost or performance optimization plus high volume prices available on request.

    Depending on the customer design, additional cooling might be required.

Block Diagram

  • 2 x 100 MBit Ethernet transceiver (PHY)
  • Board to Board (B2B)
    • Plug-on module with 3 x 80-pin Samtec Micro Tiger Eye(TM) high-speed connectors
  • I/O Interface
    • 42x MIO
    • 200x HR
    • 128x PS IO
    • 0x GTP Transceiver
    • 0x GTX Transceiver
  • Power Supply
    • 12 V power supply with watchdog
  • Others:
    • Dimensions: 6 x 6 cm
    • Rugged for shock and high vibration
    • On-board high-efficiency DC-DC converters
    • System management and power sequencing
    • eFUSE bit-stream encryption
    • AES bit-stream encryption
    • Evenly-spread supply pins for good signal integrity

Block Diagram

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draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramNameTE0728_OV_BD
simpleViewerfalse

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titleTE0728 block diagram
Scroll Ignore

draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramDisplayNameTE0728
lboxtrue
revision15
diagramNameTE0728
simpleViewerfalse
width600
linksauto
tbstylehidden
lboxtrue
diagramWidth641
revision25882


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Main Components

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draw.io Diagram
border

true

false
viewerToolbartrue
fitWindowfalse

diagramDisplayNamelbox

revision38

diagramNameTE0728_MC2
simpleViewer

false

true

width600

linksauto
tbstylehidden
lboxfalse
diagramWidth

1173

633
revision50


Scroll Only
scroll-pdftrue
scroll-officetrue
scroll-chmtrue
scroll-docbooktrue
scroll-eclipsehelptrue
scroll-epubtrue
scroll-htmltrue
draw.io Diagram
bordertrue
viewerToolbartrue
fitWindowfalse
diagramDisplayName
lboxtrue
revision38
diagramNameTE0728_MC2
simpleViewerfalse
width600
linksauto
tbstylehidden
diagramWidth1173

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  1. DDR3 SDRAM512 MByte DDR3 SDRAM, Cypress DDR3 Memory, U1
  2. Xilinx Automotive XA7Z020-1CLG484Q ,U2
  3. 100 MBit Ethernet transceiver  DP83848transceiver, U3
  4. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U4
  5. Standard Clock Oscillators @ 25MHz 3.3V, SiTime SiT1618AA, U5
  6. 1.5 A Low Dropout Linear Regulator, Texas Instruments, TPS74801-Q1, U6
  7. Real Time Clock, Micro Crystal @32.768 MHz, 3.3V, RV-3029-C3, U7
  8. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U8
  9. 3.5V to 60V step-down converter, Texas Instruments TPS54260-Q1, U9
  10. 100 MBit Ethernet transceiver  DP83848MPHPEP, U10
  11. 64 Kbit I2C EEPROM, 24LC64, U11
  12. Low-Quiescent-Current Proggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U12
  13. 16 MByte QSPI Nor Flash memory, Cypress S25FL127, U13
  14. Standard Clock Oscillators @ 50MHz 3.3V, SiTime SiT8918AA, U14
  15. Low-Quiescent-Current Priggrammable Delay Supervisory Circuit, Texas Instruments TPS3808G01-Q1, U15
  16. CAN Tranceiver, Texas Instruments SN65HVD230Q1, U16
  17. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM2
  18. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM3
  19. B2B connector  Samtec Micro Tiger Eye Connector  SEM-140-02-03, JM1
  20. User LED Green

Initial Delivery State

  1. 100 MBit Ethernet transceiver, U10
  2. User LED Green, D4
  3. Real Time Clock, U7
  4. Standard Clock Oscillators, U5
  5. 64 Kbit I2C EEPROM, U11
  6. CAN Tranceiver, U16
  7. QSPI NOR Flash memory, U13
  8. Standard Clock Oscillators, U14
  9. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U15
  10. Low-Quiescent-Current Programmable Delay Supervisory Circuit, U12
  11. B2B connector , JM2
  12. B2B connector , JM3
  13. B2B connector , JM1

FPGA (U2), DDR3 SDRAM (U1) and QSPI (U13) can be  varied on other assembly option, for more information contact us. 

Initial Delivery State

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Storage

device name

Device

Symbol

Content

Notes

Quad SPI Flash

U13
Empty

Not Programmed

DDR3 SDRAM
EEPROM
U1
U11
Empty24LC64U11

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Not Programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables,

Boot Process


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MODE

Signal

State

Boot Mode

High or open

QSPI

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

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FPGA BankPinB2BSignal StateBoot Mode

Boot_R

500

E4

J2-11

Low

QSPI

HighSD Card



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Signal

B2BI/ONote

Reset

J2-7InputComes from Carrier
RST_OUTJ2-9OutputPS_PROB_B


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

Board to Board (B2B) I/Os

TE0728 Module has 3 B2B connectors and every connector has 80 pins (2 row, 40 pins).

FPGA bank number and number of I/O signals connected to the B2B connector:

JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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FPGA BankType
JTAG Signal
B2B
Pin
TMSJM2-12
TDIJM2-10
TDOJM2-8
TCKJM2-6

PS7 UART

There is no fixed mapping for PS7 UART, if needed it can be mapped to free pins from MIO1 Bank or via EMIO to PL pins.

Recommended mapping for primary (console, debug) UART are MIO52, MIO53 for all cases when MIO1 is not used for off-board Gigabit ETH PHY.

On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
ConnectorI/O Signal CountVoltage LevelNotes
13HRJ148 Single ended (24 Diff)VCCO_13variable from carrier
500MIOJ14 Singel ended3.3V
501MIOJ238 Singel endedVMIO1variable from carrier
33HRJ334 Single ended (17 Diff)3.3V
35HR

J3

J2

20 Single ended (10 Diff)

22 Single ended (11 Diff)

3.3V


Ethernet PHY

Ethernet pins connections to Board to Board (B2B). Ethernet components ETH1 and ETH2 are connected to B2B connector J3.

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Chip/InterfaceICPS7 PeripheralNotes
SPI FlashS25FL127SABMFV10QSPI016 MByte Flash
I2C EEPROM24LC64I2C064 KByte EEPROM
RTC I2CRV-3029I2C0RTC InterruptRV-3029GPIO - MIO0User LEDLED GreenGPIO - MIO7

16 MByte Quad SPI Flash MemoryTable 5: On board Peripherals

On-board QSPI flash memory S25FL127SABMFV10 is used to store initial FPGA configuration. Datasheet is provided in Texas Instruments. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency used.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

SchematicETH1ETH2DirectionNotes
CTREFJ3-57J3-25InMagnetics center tap voltage
TD+J3-58J3-28OutTransfer
TD-J3-56J3-26Out
RD+J3-52J3-22InReceive
RD-J3-50J3-20In
LED1J3-55J3-23OutLED Yellow on carrier, multiple usage-ACK
LED2J3-53J3-21Out
LED3J3-51J3-19OutLED Green on carrier, multiple usage-Link
POWERDOWN/INTL21R20In
RESET_NM15R16InActive low PHY Reset


CAN PHY

CAN pins connections to Board to Board (B2B).

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MIO Pin
Schematic
Schematic
B2B
U13 Pin
DirectionNotes
MIO1SPI_CSA1MIO2SPI_DQ0/M0A2MIO3SPI_DQ1/M1F6MIO4SPI_DQ2/M2E4MIO5SPI_DQ3/M3A3MIO6SPI_SCK/M4A4

Supply Voltage: 2.7V to 3.6VTable 6: Quad SPI interface MIOs and pins

 Temperature Range:

  • Industrial (-40°C to +85°C)
  • Industrial Plus (-40°C to +105°C)
  • Automotive AEC-Q100 Grade 3 (-40°C to +85°C)
  • Automotive AEC-Q100 Grade 2 (-40°C to +105°C)

RTC I2C

The RV-3029-C3 is an ultra miniature Real-Time-Clock Module with embedded Crystal. This RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy of ± 6ppm from -40°C to +85°C and ± 8ppm from -40°C to +125°C.

...

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titleI2C interface MIOs and pins
CANH/CANLJ1-2/J1-4Inout/Inout


JTAG Interface

JTAG access to the Xilinx XA7Z020 FPGA through B2B connector JM2.

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JTAG Signal

B2B Pin

TMSJ2-12
TDIJ2-10
TDOJ2-8
TCKJ2-6


MIO Pins

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MIO PinConnected toB2BNotes
MIO0MIO0-RTC interrupt
MIO1...MIO6

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

-SPI Flash
MIO7LED RED-LED
MIO8/MIO9Tx/Rx-CAN Transceiver
MIO10...MIO13IO_0 ... IO_3J1GPIO
MIO14/MIO15SCL/SDA-I2C
MIO16...MIO39-J2GPIO
MIO40...MIO48CLK, Cmd, Data0...Data3, wp, cdJ2SD
MIO48PS_MIO48_501J2LED Red on Carrier
MIO49PS_MIO49_501J2LED Yellow on Carrier
MIO50PS_MIO49_501J2LED Green on Carrier
MIO51PS_MIO51_501J2GPIO
MIO52/MIO53UART_Txd / UART_RxdJ2UART transfer/recieve


On-board Peripherals

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  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transceiver PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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I2C EEPROM

The Microchip Technology Inc. 24LC64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. Lowvoltage design permits operation down to 1.7V, with standby and active currents of only 1 μA and 3 mA, respectively. It has been developed for advanced, lowpower applications such as personal communications or data acquisition. The 24LC64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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MIO PinSchematicU11 PinNotes
MIO15SDA3On-board RTC, and EEPROM
MIO14SCL1On-board RTC, and EEPROM

LEDs

...

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titleOn-board LEDs

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Chip/InterfaceDesignatorNotes
QSPI FlashU13---
EEPROMU11EEPROM
RTCU7Real Time Clock
DDR3 SDRAMU1Volatile Memory
EthernetU3, U10Two 100 Mbit Ethernet PHY
CAN TransceiverU16---
User LEDD4Green LED
OscillatorsU14, U7, U5Clock Sources


Quad SPI Flash Memory

On-board QSPI flash memory is used to store initial FPGA configuration. Besides FPGA configuration, remaining free flash memory can be used for user application and data storage. All four SPI data lines are connected to the FPGA allowing x1, x2 or x4 data bus widths. Maximum data rate depends on the selected bus width and clock frequency.

Quad SPI Flash (U7) is connected to the Zynq PS QSPI0 interface via PS MIO bank 500.

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MIO PinSchematicNotes
MIO1SPI_CS
MIO2SPI_DQ0/M0
MIO3SPI_DQ1/M1
MIO4SPI_DQ2/M2
MIO5SPI_DQ3/M3
MIO6SPI_SCK/M4


RTC 

The RTC has an I2C Bus (2-wire SerialInterface) and offers temperature compensated time. The STC-Smart Temperature Compensation is calibrated in the factory and leads to a very high time-accuracy.

RTC interrupt is connected to MIO0 connected to Bank 500 through pin G6.

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...

The TE0728 SoM has two 512 GByte volatile DDR3 SDRAM IC for storing user application code and data.

  • Part number: NT5CC256M16DP Nanya
  • Supply voltage: 1.35V
  • Speed: 1600 Mbps
  • NOR Flash
  • Temperature: -40°C ~95°C 

 Configuration of the DDR3 memory controller in the FPGA should be done using the MIG tool in the Xilinx Vivado Design Suite IP catalog.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet  DP83848-EP are provided by Texas Instrument on the board. Datasheet is provided TI website, Literature number SNLS208H. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz source is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

Both PHY's must be operated in MII Mode, other modes are not supported. It is possible to use PS ENET0 or ENET1 via EMIO routing or Ethernet IP Cores implemented in PL Fabric.

Pullup
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Schematic
MIO Pin
ETH1ETH2
I2C AddressDesignatorNotes
CTREFJ3-57J3-25Magnetics center tap voltageTD+J3-58J3-28on-boardTD-J3-56J3-26on-boardRD+J3-52J3-22on-boardRD-J3-50J3-20on-boardLED1J3-55J3-23on-boardLED2J3-53J3-21on-boardLED3J3-51J3-19on-boardPOWERDOWN/INTL21R20on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output driving 1 if Interrupt not used.RESET_NM15R16on-chipIt is recommended to configure FPGA I/O as input with Pullup or as output (active low PHY Reset).

...

MIO14...150x56U7Slave address


EEPROM

The Microchip Technology Inc. 24xx64 is a 64 Kbit Electrically Erasable PROM. The device is organized as a single block of 8K x 8-bit memory with a 2-wire serial interface. The 24xx64 also has a page write capability for up to 32 bytes of data. Functional address lines allow up to eight devices on the same bus, for up to 512 Kbits address space.

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MIO PinI2C AddressDesignatorNotes
MIO14...150x50U11Slave address


LEDs

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DesignatorColorConnected toActive Level
D9GreenDONELow
D8REDMIO7High
D4GreenBank 33 - V18High


DDR3 SDRAM

The TE0728 SoM has a volatile DDR3 SDRAM, 256Mx16bit (512MB), IC for storing user application code and data. Size of DDR3 can be varied in different assembly versions.

  • Part number: NT5CB256M16CP-DIH
  • Supply voltage: 1.5V
  • Organization: 256M x 16 bits

DDR3 SDRAM can be varied on demand for other assembly options. DDR3 can have density of maximum 512MB due to available addressing. The maximum possible speed for DDR3 SDRAM is 1066 Mb/s.

Ethernet

There are two 100 MBit Extreme Temperature Ethernet provided by Texas Instrumen on the board. Datasheet is provided at TI website. Both PHY's are connected with all I/O Pins to FPGA Bank 34 (VCCIO = 3.3V). PHY Clock 25 MHz sources is provided from MEMS Oscillator. There is no sharing of signals for the two PHY's.

PUDC pin is connected with pull-up to 3.3V those pre-configuration pull-ups are disabled by default. Strapping resistor exist to change the PUDC mode.

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When connecting the PHY's to Zynq PS ETH0, ETH1 EMIO GMII Interfaces it is recommended to use GMII to MII Wrap IP Core. This IP core maps the EMIO GMII to external MII Interface.

CAN Transceiver

The SN65HVD230Q,  controller area network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is avaiable in Texas Instrumens website. They are intended for use in applications employing the CAN serial communication physical layer in accordance with the ISO 11898 standard. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. Temperature must be in range of -40°C ~125°C .

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titleCAN Tranciever interface MIOs

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MIO Pin
Bank
Schematic
Signal Name
U16 Pin
ETH1
Notes
ETH2
MIO8
Signal Description
D
34
1
ETH-RST
MIO9
M15
R4

Low Quiescent Current Programmable Delay Supervisory Circuit

The TPS3808G01-Q1 microprocessor supervisory circuits monitor system voltages from 0.4 V to 5 V, asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the useradjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

The TPS3808G01-Q1 device uses a precision reference to achieve 0.5% threshold accuracy for VIT ≤ 3.3 V. The reset delay time can be set to 20 ms by disconnecting the CT pin, 300 ms by connecting the CT pin to VDD using a resistor, or can be useradjusted from 1.25 ms to 10 s by connecting the CT pin to an external capacitor. The TPS3808G01-Q1 has a very low typical quiescent current of 2.4 μA, so it is well suited for battery-powered applications. 

Low Dropout Linear Regulator

The TPS74801-Q1 low-dropout (LDO)  provides an easy-to-use robust power management  solution for a wide variety of applications. User programmable soft-start minimizes stress on the input power source by reducing capacitive inrush current on start-up. The soft-start is monotonic and well- suited for powering many different types of Monitoring or Provides a Sequencing Signal processors and ASICs. The enable input and power for Other Supplies good output allow easy sequencing with external regulators. This complete flexibility permits the user to configure a solution that meets the sequencing Voltage Startup requirements of FPGAs, DSPs, and other applications with special start-up requirements.

A precision reference and error amplifier deliver 2% accuracy over load, line, temperature, and process. The device is stable with any type of capacitor greater than or equal to 2.2 μF, and is fully specified SON-10 and 5 x 5 QFN-20 Packages from –40°C to 105°C for the DRC package, and from –40°C to 125°C for the RGW package.

Clock Sources

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anchorTable_OBP_CLK
titleOsillators

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Power Supply

Power supply with minimum current capability of 3.5 A for system startup is recommended.

Power Consumption

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anchorTable_PWR_PC
titlePower Consumption

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Power Distribution Dependencies

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anchorFigure_PWR_PD
titlePower Distribution
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Power-On Sequence

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anchorFigure_PWR_PS
titlePower Sequency
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R16Ethernet reset, active-low.
34ETH_COLL16P20
34MDCP16T17

Ethernet management clock.

34MDIOM16T16Ethernet management data.
34ETH_TX_D0J22N22Ethernet transmit data 0. Output to Ethernet PHY.
34ETH_TX_D1M17P21Ethernet transmit data 1. Output to Ethernet PHY.
34ETH_TX_D2K21P22Ethernet transmit data 2. Output to Ethernet PHY.
34ETH_TX_D3M22R21Ethernet transmit data 3. Output to Ethernet PHY.
34ETH_TX_ENJ21M21Ethernet transmit enable.
34ETH_RX_D0L17R18Ethernet receive data 0. Input from Ethernet PHY. 
34ETH_RX_D1K18R19Ethernet receive data 1. Input from Ethernet PHY. 
34ETH_RX_D2J18T18Ethernet receive data 2. Input from Ethernet PHY. 
34ETH_RX_D3J20T19Ethernet receive data 3. Input from Ethernet PHY. 
34ETH_RX_DVN17P15Ethernet receive data valid.


CAN Transceiver

Controller Area Network (CAN) transceivers are designed for use with the Texas Instruments TMS320Lx240x 3.3-V DSPs with CAN controllers. The datasheet is available in TI website. Each CAN transceiver is designed to provide differential transmit capability to the bus and differential receive capability to a CAN controller at speeds up to 1 Mbps. 

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titleCAN Tranciever interface MIOs

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BankSignal nameNotes
500D - TxDriver Input
500R - RxReciever Output


Oscillators

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titleOsillators

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DesignatorDescriptionFrequencyUsed as
U14MEMS Oscillator50 MHzPS_CLK
U5MEMS Oscillator25 MHzEthernet PHY Clock
U7RTC (internal oscillator)32.768 KHzCLKOUT of RTC is not connected


Power and Power-On Sequence

Power Supply

Power supply with minimum current capability of 2.5A for system startup is recommended.

Power Consumption

The PS and PL power supplies are fully independent. PS power supplies (VCCPINT, VCCPAUX, VCCPLL, VCCO_DDR, VCCO_MIO0, and VCCO_MIO1) can be powered before or after any PL power supplies. The PS and PL power regions are isolated to prevent damage. The recommended power-on sequence is VCCPINT, then VCCPAUX and VCCPLL together, then the PS VCCO supplies (VCCO_MIO0, VCCO_MIO1, and VCCO_DDR) to achieve minimum current draw and ensure that the I/Os are 3-stated at power-on. The PS_POR_B input is required to be asserted to GND during the power-on sequence until VCCPINT, VCCPAUX and VCCO_MIO0 have reached minimum operating levels to ensure PS eFUSE integrity.

Voltage Monitor Circuit

...

Scroll Title
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titleModule power rails.Power Consumption

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Power
Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotesVIN1,3--InputVMIO-2-I/O3.3V19425,57Output

1.8V

-5-Output

Bank Voltages

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anchorTable_PWR_BV
titleZynq SoC bank voltages.

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Bank          

...

Voltage

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VCCO_MIO1_500

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Supplied by the carrier board. JM2,JM3

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hiddentrue
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Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Dependencies


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borderfalse
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revision8


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Power on Sequence

The TE07028 SoM meets the recommended criteria to power up the Xilinx Zynq properly by keeping a specific sequence of enabling the on-board DC-DC converters and regulators dedicated to the particular functional units of the Zynq chip and powering up the on-board voltages. When the U8 and U9 generates PWRGD signal, it turns on the U4 which generates PWRGD_3.3V, it turns on the U6 and it generates PWROK signal which is connected to MR. Whenever the supply voltage for U12 drops down below the threshold it resets the system. Actually it resets the system when all regulators are working.

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titlePower On Sequence


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draw.io Diagram
borderfalse
viewerToolbartrue
fitWindowfalse
diagramNameTE0728_PWR_PS
simpleViewerfalse
linksauto
tbstylehidden
lboxtrue
diagramWidth649
revision7


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Voltage Monitor Circuit

The microprocessor supervisory circuits monitor system voltages asserting an open-drain RESET signal when the SENSE voltage drops below a preset threshold or when the manual reset (MR) pin drops to a logic low. The RESET output remains low for the user adjustable delay time after the SENSE voltage and MR return above their thresholds. Datasheet is available in Texas Instruments website.

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titleVoltage Monitor Circuit


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borderfalse
viewerToolbartrue
fitWindowfalse
diagramNameTE0728_PWR_VMC
simpleViewerfalse
linksauto
tbstylehidden
lboxtrue
diagramWidth644
revision4



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Power Rails

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6 x 6 modules use two or three Samtec Micro Tiger Eye Connector on the bottom side.

  • 3 x REF-189018-01 (compatible to SEM-140-02-03.0-H-D-A), (80 pins, "40" per row)

    Operating Temperature:-55°C ~ 125°C
    Current Rating: 2.6A per ContactNumber of Positions: 80
    Number of Rows: 2

Absolute Maximum Ratings

Processing System(PS)

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anchorTable_TS_AMR_PS
titlePS absolute maximum ratings

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titlePL absolute maximum ratingsModule power rails.

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SymbolsDescriptionMinMaxUnit
VCCINTPL internal logic supply voltage-0.51.1V
VCCPAUXPL auxiliary supply voltage-0.52.0V
VCCPLLPL PLL supply-0.51.1V
VPREFPL input reference voltage-0.52.0V
VCCOPL supply voltage for HR I/O banks-0.53.6V
VINI/O input voltage for HR I/O banks1.713.45V

Technical Specifications

Absolute Maximum Ratings

Power Signal

B2B

JM1 Pin

B2B

JM2 Pin

B2B

JM3 Pin

DirectionNotes
VIN1,3--InputSupply voltage from carrier board.
VCCO_1339--Input
VBATT-1-OutputRTC Supply voltage
3.3V19425,57OutputInternal 3.3V voltage level.
VMIO

-

2
InputVariable and supplied by carrier

1.8V

-5-OutputInternal 1.8V voltage level.


Bank Voltages

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titleModule absolute maximum ratingsZynq SoC bank voltages.

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ParameterMinMaxUnitsReference Document
VIN supply voltage3.560VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks1.713.465VSee Xilinx DS187 datasheet.
I/O input voltage for PS MIO banks-0.2VCCO_MIO + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.
I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.
Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.
I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.
Storage Temperature-65150°CSee Xilinx DS187 datasheet.
CAN Transceiver Temperature-40125°CSee Texas Instrument sn65hvd230q-q1 datasheet.
SPI Flash Memory-4085°CSee Cypress S25FL127S datasheet.
DDR3 SDRAM Temperature-4095°C

See Nanya NT5CC256M16CP-DIA datasheet.

...

Commercial grade: 0°C to +70°C.

Industrial and automotive grade: -40°C to +85°C.

...

Bank          

Schematic Name

Voltage

I/O TypeNotes
500VCCO_MIO0_5003.3VMIO
501

VCCO_MIO1_501

2.5V or 3.3VMIOsupplied by carrier.
502VCCO_DDR_5021.5VDDR3
13VCCO_131.8V or 3.3VHRSupplied by the carrier board. J1
333.3V3.3VHRSupplied by carrier board. J3
343.3V3.3VHR


353.3V3.3VHR

Supplied by the carrier board. J2, J3


Board to Board Connectors

Page properties
hiddentrue
idComments
  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series, for example: 4 x 5 SoM LSHM B2B Connectors

    Include Page
    6 x 6 SoM LSHM B2B Connectors
    6 x 6 SoM LSHM B2B Connectors

Include Page
6 x 6 SoM TEM and SEM B2B Connectors
6 x 6 SoM TEM and SEM B2B Connectors

Technical Specifications

Absolute Maximum Ratings

1.71
Scroll Title
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titleRecommended operating conditions.Absolute maximum ratings

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Parameter
SymbolsMinMax
Units
Unit
Reference Document
Description
VIN supply voltage-0.3
.5
60
65VTPS54260-Q1 datasheets.
Supply voltage for PS MIO banks
VMIO-0.53.
465
6V
See Xilinx DS187 datasheet.
PS MIO I/O
input voltage for PS MIO banks
supply voltage
VCCO-0.
2VCCO_MIO + 0.20
53.6V
See Xilinx DS187 datasheet.Supply voltage for PS DDR1.141.89VSee Xilinx DS187 datasheet.I/O input voltage for PS DDR-0.20VCCO_DDR + 0.20VSee Xilinx DS187 datasheet.Supply voltage for HR I/Os banks1.143.465VSee Xilinx DS187 datasheet.I/O input voltage for HR I/O banks-0.20VCCIO + 0.20VSee Xilinx DS187 datasheet.Storage Temperature-65150°CSee Xilinx DS187 datasheet.CAN Transceiver Temperature-40125°CSee Texas Instrument sn65hvd230q-q1 datasheet.SPI Flash Memory-4085°CSee Cypress S25FL127S datasheet.DDR3 SDRAM Temperature-4095°C

See Nanya NT5CC256M16CP-DIA datasheet.