Page properties |
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Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board"
Date | Version | Changes | Author |
---|
20222023- | 0812- | 2414 | 3.1. | 11Modification from link "available short link"17 | - updated according to Vivado 2023.2
| ma | 2022 2023- | 0106- | 2513 | 3.1. | 10- removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 16 | - Design flow:
- added alternative programming files in Petalinux
- added chapter FSBL Patch in Software Design - Petalinux
| ma | 2023-06-01 | 2022-01-14 | 3.1. | 9extended notes for microblaze boot process with linux15 | | add u. | to petalinux notesadd dtb to prebuilt contentreplace 20.2 with 21.2jh | 2021-06-28 | ma | 2023-06-01 | 3.1.14 | - expandable lists for revision history and supported hardware
| wh | 2023-05-25 | 3.1. | 8- added boot process for Microblaze
- minor typos, formatting
| ma | 13 | - updated according to Vivado 2022.2
| ma | 2023-02-08 | 2021-06-01 | 3.1. | 7 | jh | 2021-05-0412 | - removed content of
- Special FSBL for QSPI programming
| ma | 2022-08-24 | 3.1. | 611 | removed zynq_ from zynq_fsbl- Modification from link "available short link"
| ma | 2021 2022- | 0401- | 2825 | 3.1. | 5- added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-2710 | - removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 2022-01-14 | 3.1. | 4- Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
| ma | 3.1.3 | | ma | 3.1.2 | - minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.scr description
- added USB for programming
| ma | 3.1.1 | - swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
| ma | 3.1 | - Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
| 3.0 | - add fix table of content
- add table size as macro
- removed page initial creator
|
|
9 | - extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
| jh | 2021-06-28 | 3.1.8 | - added boot process for Microblaze
- minor typos, formatting
| ma | 2021-06-01 | 3.1.7 | | jh | 2021-05-04 | 3.1.6 | - removed zynq_ from zynq_fsbl
| ma | 2021-04-28 | 3.1.5 | - added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-27 | 3.1.4 | - Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
| ma |
| 3.1.3 | | ma |
| 3.1.2 | - minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.scr description
- added USB for programming
| ma |
| 3.1.1 | - swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
| ma |
| 3.1 | - Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
|
|
| 3.0 | - add fix table of content
- add table size as macro
- removed page initial creator
|
|
|
Page properties |
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
|
Page properties |
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Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
|
Overview
Scroll Ignore |
---|
scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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|
Zynq Design PS with Linux and simple frequency counter to measure MGT Reference CLK with Vivado HW-Manager.
Refer to http://trenz.org/te0745-info for the current online version of this manual and other available documentation.
Key Featuresonline version of this manual and other available documentation.
Key Features
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Notes : - Add basic key features, which can be tested with the design
|
Excerpt |
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- Vitis/Vivado 2023.2
- PetaLinux
- SD
- ETH (MAC from EEPROM)
- USB
- I2C
- RTC
- FMeter
- Modified FSBL for SI5338 programming
|
Revision History
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Notes : - add every update file on the download
- add design changes on description
|
Expand |
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Scroll Title |
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anchor | Table_DRH |
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title-alignment | center |
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title | Design Revision History |
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| Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
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|
Date | Vivado | Project Built | Authors | Description |
---|
2024-02-20 | 2023.2 | TE0745-test_board-vivado_2023.2-build_4_20240220094718.zip TE0745-test_board_noprebuilt-vivado_2023.2-build_4_20240220094718.zip | Manuela Strücker | - update 2023.2
- new assembly variants
| 2023-04-25 | 2021.2.1 | TE0745-test_board-vivado_2021.2-build_20_20230425125003.zip TE0745-test_board_noprebuilt-vivado_2021.2-build_20_20230425125003.zip | Manuela Strücker | | 2023-02-07 | 2021.2.1 | TE0745-test_board-vivado_2021.2-build_20_20230207205537.zip TE0745-test_board_noprebuilt-vivado_2021.2-build_20_20230207205537.zip | Manuela Strücker | - update 2021.2
- new assembly variants
- added jtag2axi for test purposes
| 2020-03-30 | 2019.2 | TE0745-test_board-vivado_2019.2-build_8_20200330083452.zip TE0745-test_board_noprebuilt-vivado_2019.2-build_8_20200330083503.zip | John Hartfiel | - 2019.2 update
- FSBL rework, SI5338 Project with Clock Builder pro
- device tree update
- Vitis support
- new assembly variants
| 2018-09-2019 | 2018.2 | TE0745-test_board_noprebuilt-vivado_2018.2-build_04_20190918103545.zip TE0745-test_board-vivado_2018.2-build_04_20190918103531.zip | John Hartfiel | - BUGFIX in TE0745-02-45-3EA board parts
| 2018-11-26 | 2018.2 | TE0745-test_board-vivado_2018.2-build_03_20181126115131.zip TE0745-test_board_noprebuilt-vivado_2018.2-build_03_20181126115320.zip | John Hartfiel | - Rework Board Part Files
- New assembly versions
- Rework BD Design
- add init.sh scripts
| 2017-10-23 | 2017.2 | TE0745-test_board_noprebuilt-vivado_2017.2-build_05_20171023171903.zip TE0745-test_board-vivado_2017.2-build_05_20171023171855.zip | John Hartfiel | |
|
|
Release Notes and Know Issues
Page properties |
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Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
|
Scroll Title |
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anchor | Table_KI |
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title-alignment | center |
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title | Known Issues |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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style | |
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widths | |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
Issues | Description | Workaround | To be fixed version |
---|
QSPI programming | QSPI programming is not possible in other boot modes than JTAG. | - use JTAG boot mode for QSPI programming
- When using the carrier board TEB0745, use the optional firmware to get into JTAG boot mode.
| --- |
|
Requirements
Software
Page properties |
---|
|
Notes : - Add basic key features, which can be tested with the design
|
Excerpt |
---|
- Vitis/Vivado 2021.2.1
- PetaLinux
- SD
- ETH (MAC from EEPROM)
- USB
- I2C
- RTC
- FMeter
- Modified FSBL for SI5338 programming
|
Revision History
- list of software which was used to generate the design
|
Scroll Title |
---|
anchor | Table_SW |
---|
title-alignment | center |
---|
title | Software |
---|
|
Scroll Table Layout |
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orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Software | Version | Note |
---|
Vitis | 2023.2 | needed, Vivado is included into Vitis installation | PetaLinux | 2023.2 | needed | SI ClockBuilder Pro | --- | optional |
|
Hardware
Page properties |
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|
Notes : add every update file on the downloadadd design changes on description- list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Expand |
---|
|
| DRHHWM | title-alignment | center |
---|
title |
---|
|
| Design Revision History | Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
|
|
Date | Vivado | Project Built | Authors | Description |
---|
2023-02-07 | 2021.2.1 | TE0745-test_board-vivado_2021.2-build_20_20230207205537.zip TE0745-test_board_noprebuilt-vivado_2021.2-build_20_20230207205537.zip | Manuela Strücker | - update 2021.2
- new assembly variants
- added jtag2axi for test purposes
|
2020-03-30 | 2019.2 | TE0745-test_board-vivado_2019.2-build_8_20200330083452.zip TE0745-test_board_noprebuilt-vivado_2019.2-build_8_20200330083503.zip | John Hartfiel | - 2019.2 update
- FSBL rework, SI5338 Project with Clock Builder pro
- device tree update
- Vitis support
- new assembly variants
|
2018-09-2019 | 2018.2 | TE0745-test_board_noprebuilt-vivado_2018.2-build_04_20190918103545.zip TE0745-test_board-vivado_2018.2-build_04_20190918103531.zip | John Hartfiel | - BUGFIX in TE0745-02-45-3EA board parts
|
2018-11-26 | 2018.2 | TE0745-test_board-vivado_2018.2-build_03_20181126115131.zip TE0745-test_board_noprebuilt-vivado_2018.2-build_03_20181126115320.zip | John Hartfiel | - Rework Board Part Files
- New assembly versions
- Rework BD Design
- add init.sh scripts
|
2017-10-23 | 2017.2 | TE0745-test_board_noprebuilt-vivado_2017.2-build_05_20171023171903.zip TE0745-test_board-vivado_2017.2-build_05_20171023171855.zip | John Hartfiel | |
Release Notes and Know Issues
Page properties |
---|
|
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
|
Scroll Title |
---|
anchor | Table_KI |
---|
title-alignment | center |
---|
title | Known Issues |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Issues | Description | Workaround | To be fixed version |
---|
QSPI programming | QSPI programming is not possible in other boot modes than JTAG. | - use JTAG boot mode for QSPI programming
- When using the carrier board TEB0745, use the optional firmware to get into JTAG boot mode.
| --- |
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|
TE0745-02-30-1I | 30_1i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | less MGT | TE0745-02-30-2IA | 30_2i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | less MGT | TE0745-02-35-1C | 35_1c_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0745-02-45-1C | 45_1c_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0745-02-45-1CA | 45_1c_1gb | REV02|REV01 | 1GB | 64MB | NA | NA | NA | TE0745-02-45-2I | 45_2i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | NA | TE0745-02-45-2IA | 45_2i_1gb | REV02|REV01 | 1GB | 64MB | NA | NA | NA | TE0745-02-45-3EA | 45_3e_1gb | REV02|REV01 | 1GB | 64MB | NA | NA | NA | TE0745-02-71I11-A | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | less MGT | TE0745-02-71I11-AK | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | less MGT | TE0745-02-71I31-A | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | less MGT | TE0745-02-71I31-AK | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | less MGT | TE0745-02-71I31-AZ | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | less MGT | TE0745-02-72I11-A | 30_2i_1gb | REV02 | 1GB | 64MB | NA | NA | less MGT | TE0745-02-72I31-A | 30_2i_1gb | REV02 | 1GB | 64MB | NA | NA | less MGT | TE0745-02-72I31-AZ | 30_2i_1gb | REV02 | 1GB | 64MB | NA | NA | less MGT | TE0745-02-81C11-A | 35_1c_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-81C31-A | 35_1c_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-81C31-AZ | 35_1c_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-82I31-A | 35_2i_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-91C11-A | 45_1c_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-91C31-A | 45_1c_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-91C31-AZ | 45_1c_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-92I11-A | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-92I11-F | 45_2i_ff_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-92I31-A | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-92I31-AK | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-92I31-AZ | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-92I31-B | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-93E11-A | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-93E11-KA | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-93E31-A | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-93E31-AK | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-93E31-AZ | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | NA | TE0745-02-S003 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | C | TE0745-02-S005 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | C;less MGT | TE0745-02-S006 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | without RTC | C;less MGT | TE0745-02-S007C1 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | without PLL | CF | TE0745-02-S007C2 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | without PLL | CF | TE0745-02-S007C3 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | without PLL | CF | TE0745-02-S008 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | C;less MGT | TE0745-02-S009 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | C;less MGT | TE0745-02-S012 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | without PLL | C | TE0745-02-S013 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | without PLL | C | TE0745-02-S014C1 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | without PLL | C | TE0745-02-S014C2 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | without PLL | C | TE0745-02-S014C3 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | without PLL | C | TE0745-02-S016 | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | C | TE0745-02-S017 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | C;less MGT | TE0745-02-S018 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | C;less MGT | TE0745-02-S019 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | C | TE0745-02-S020 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | C | TE0745-02-S021 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | C | TE0745-02-S022 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | C | TE0745-02-S024 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | C | TE0745-03-71I31-A | 30_1i_1gb | REV03 | 1GB | 64MB | NA | NA | less MGT | TE0745-03-71I31-AK | 30_1i_1gb | REV03 | 1GB | 64MB | NA | NA | less MGT | TE0745-03-72I31-A | 30_2i_1gb | REV03 | 1GB | 64MB | NA | NA | less MGT | TE0745-03-81C31-A | 35_1c_1gb | REV03 | 1GB | 64MB | NA | NA | NA | TE0745-03 |
|
|
Requirements
Software
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Scroll Title |
---|
anchor | Table_SW |
---|
title-alignment | center |
---|
title | Software |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Software | Version | Note |
---|
Vitis | 2021.2.1 | needed, Vivado is included into Vitis installation |
PetaLinux | 2021.2 | needed |
SI ClockBuilder Pro | --- | optional |
Hardware
Page properties |
---|
|
Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on "<project folder>\board_files\*_board_files.csv"
Design supports following modules:
Scroll Title |
---|
anchor | Table_HWM |
---|
title-alignment | center |
---|
title | Hardware Modules |
---|
|
Scroll Table Layout |
---|
|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|
TE0745-02-30-1I | 30_1i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-30-2IA | 30_2i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-35-1C | 35_1c_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | TE0745-02-45-2I | 45_2i_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | TE0745-02-45-2IA | 45_2i_1gb | REV02|REV01 | 1GB | 64MB | NA | NA | TE0745-02-45-1C* | 45_1c_1gb | REV02|REV01 | 1GB | 32MB | NA | NA | TE0745-02-45-1CA | 45_1c_1gb | REV02|REV01 | 1GB | 64MB | NA | NA | TE0745-02-45-3EA | 45_3e_1gb | REV02|REV01 | 1GB | 64MB | NA | NA | TE0745-02-93E11-A | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-92I11-F | 45_2i_ff_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-92I11-A | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-91C11-A | 45_1c_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-81C11-A | 35_1c_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-72I11-A | 30_2i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-71I11-A | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-71I11-AK | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-71I31-A | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-71I31-AK | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-72I31-A | 30_2i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-81C31-A | 35_1c_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-91C31-A | 45_1c_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-92I31-A | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-92I31-AK | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-92I31-B | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-93E11-KA | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-93E31-A | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-93E31-AK | 45_3e_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-S003 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | TE0745-02-S005 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-S006 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs without RTC |
TE0745-02-S007C1 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | without PLL |
TE0745-02-S007C2 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | without PLL |
TE0745-02-S007C3 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | without PLL |
TE0745-02-S012 | 45_2i_1gb | REV02 | 1GB | 64MB | NA | NA | without PLL |
TE0745-02-S008 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02-S009 | 30_1i_1gb | REV02 | 1GB | 64MB | NA | NA | smaller FPGA has less MGTs |
TE0745-02REV02 1GB 64MB NA NA 0272I31AZ302iREV02 1GB 64MB NA NA | smaller FPGA has less MGTs02S0132iREV02 1GB 64MB NA NA 0293E31AZ3eREV0264MB NA NA 02S0163eREV0264MB NA NA 02S017301iREV0264MB NA NA | smaller FPGA has less MGTs0271I31AZ301iREV0264MB NA | NA | smaller FPGA has less MGTs
Design supports following carriers:
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Carrier Model | Notes |
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TEB0745* |
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*used as reference |
Additional HW Requirements:
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title | Additional Hardware |
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Additional Hardware | Notes |
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USB Cable for JTAG/UART | Check Carrier Board and Programmer for correct type | XMOD Programmer | Carrier Board dependent, only if carrier has no own FTDI |
*used as reference |
Content
For general structure and of the reference design, see see Project Delivery - Xilinx AMD devices
Design Sources
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Type | Location | Notes |
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation | PetaLinux | <project folder>\os\petalinux | PetaLinux template with current configuration |
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Additional Sources
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title | Additional design sources |
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Type | Location | Notes |
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SI5338 | <project folder>\misc\PLL\Si5338_B | SI5338 Project with current PLL Configuration | init.sh | <project folder>\misc\sd\ | Additional Initialization Script for Linux |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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title | Prebuilt files |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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anchor | Table_PF |
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title-alignment | center |
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title | Prebuilt files (only on ZIP with prebult content) |
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repeatTableHeaders | default |
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sortEnabled | false |
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cellHighlighting | true |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
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Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
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language | bash |
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theme | Midnight |
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title | _create_win_setup.cmd/_create_linux_setup.sh |
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
Create hardware description file (.xsa file) for PetaLinux project and export to prebuilt folder
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") |
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TE::hw_build_design -export_prebuilt |
Info |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
- Create and configure your PetaLinux project with exported .xsa-file, see PetaLinux KICKstart
- use TE Template from "<project folder>\os\petalinux"
use exported .xsa file from "<project folder>\prebuilt\hardware\<short name>" . Note: HW Export from Vivado GUI creates another path as default workspace.
The build images are located in the "<plnx-proj-root>/images/linux" directory
Configure the boot.scr file as needed, see Distro Boot with Boot.scr
- Generate Programming Files with Vitis
- Copy PetaLinux build image files to prebuilt folder
- system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
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"<project folder>\prebuilt\os\petalinux\<ddr size>" or "<project folder>\prebuilt\os\petalinux\<short name>" |
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This step depends on Xilinx Device/Hardware for Zynq-7000 series - copy u-boot.elf, system.dtb, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for ZynqMP
- copy u-boot.elf, system.dtb, bl31.elf, image.ub and boot.scr from "<plnx-proj-root>/images/linux" to prebuilt folder
for Microblaze |
Generate Programming Files
with Vitis Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") |
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TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
Note |
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TCL scripts generate also platform project, this must be done manually in case GUI is used. See Vitis |
Generate Programming Files with Petalinux (alternative), see PetaLinux KICKstart
Launch
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Note: - Programming and Startup procedure
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Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging:
Vivado/Vitis/SDSoC-Xilinx Software Programming and DebuggingGet prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select create and open delivery binary folder
Info |
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Note: Folder "<project folder>\_binaries_<Article Name>" with subfolder "boot_<app name>" for different applications will be generated |
QSPI-Boot mode
Option for Boot.bin on QSPI Flash and image.ub and boot.scr on SD or USB.
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script programs BOOT.bin on QSPI flash) |
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TE::pr_program_flash -swapp u-boot
TE::pr_program_flash -swapp hello_te0745 (optional) |
- Copy image.ub and boot.scr on SD or USB
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder,see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to QSPI-Boot and insert SD or USB.
- Depends on Carrier, see carrier TRM.
SD-Boot mode
- Copy image.ub, boot.scr and Boot.bin on SD
- use files from "<project folder>\_binaries_<Article Name>\boot_linux" from generated binary folder, see: Get prebuilt boot binaries
- or use prebuilt file location, see "<project folder>\prebuilt\file_location.txt"
- Set Boot Mode to SD-Boot.
- Depends on Carrier, see carrier TRM.
- Insert SD-Card in SD-Slot.
JTAG
Not used on this Example.
Usage
- Prepare HW like described on section Programming
- Connect UART USB (most cases same as JTAG)
Select SD Card as Boot Mode (or QSPI - depending on step 1)
Info |
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Note: See TRM of the Carrier, which is used. |
Tip |
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Starting with Petalinux version 2020.1, the industry standard "Distro-Boot" boot flow for U-Boot was introduced, which significantly expands the possibilities of the boot process and has the primary goal of making booting much more standardised and predictable. The boot options described above describe the common boot processes for this hardware; other boot options are possible. For more information see Distro Boot with Boot.scr |
Power On PCB
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1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init PS, programs PL using the bitstream and loads U-boot from SD into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR |
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This step depends on Xilinx Device/Hardware for Zynq-7000 series 1. Zynq Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for ZynqMP??? 1. ZynqMP Boot ROM loads FSBL from SD/QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from SD/QSPI into DDR, 3. U-boot loads Linux (image.ub) from SD/QSPI/... into DDR
for Microblaze with Linux
1. FPGA Loads Bitfile from Flash, 2. MCS Firmware configure SI5338 and starts Microblaze, (only if mcs is available) 3. SREC Bootloader from Bitfile Firmware loads U-Boot into DDR (This takes a while), 4. U-boot loads Linux from QSPI Flash into DDR
for native FPGA
... |
Linux
- Open Serial Console (e.g. putty)
- Speed: 115200
select COM Port
Info |
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Win OS, see device manager, Linux OS see dmesg |grep tty (UART is *USB1) |
Linux Console:
Code Block |
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language | bash |
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theme | Midnight |
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# password default disabled with 2021.2 petalinux release
petalinux login: root
Password: root |
Info |
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Note: Wait until Linux boot finished |
You can use Linux shell now.
Code Block |
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language | bash |
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theme | Midnight |
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i2cdetect -y -r 0 (check I2C 0 Bus)
dmesg | grep rtc (RTC check)
udhcpc (ETH0 check)
lsusb (USB2.0 check) |
Option Features
- Webserver to get access to Zynq
- insert IP on web browser to start web interface
- init.sh scripts
- add init.sh script on SD, content will be load automatically on startup (template included in "<project folder>\misc\SD"
- Script will enable SFP interface after linux booting, if file is copied on SD
Vivado HW Manager
Open Vivado HW-Manager and add VIO signal to dashboard (*.ltx located on prebuilt folder)Monitoring:
SI5338 CLKs:
- Set radix from VIO signals to unsigned integer.
Note: Frequency Counter is inaccurate and displayed unit is Hz, SI5338 CLK (0 and 3) are configured to 125MHz by default.
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anchor | Figure_VHM |
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title-alignment | center |
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title | Vivado Hardware Manager |
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System Design - Vivado
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Block Design
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design |
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*clk3 is not available on the smallest SOC (xc7z030) |
PS Interfaces
Activated interfaces:
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anchor | Table_PSI |
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title-alignment | center |
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title | PS Interfaces |
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orientation | portrait |
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sortDirection | ASC |
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repeatTableHeaders | default |
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sortByColumn | 1 |
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sortEnabled | false |
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Type | Note |
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DDR |
| QSPI | MIO | ETH0 | MIO | USB0 | MIO | SD0 | MIO | UART0 | MIO | I2C0 | MIO | GPIO | MIO | ETH0 Reset | MIO | USB0 Reset | MIO | I2C0 Reset | MIO | TTC0..1 | EMIO | SWDT0 | EMIO |
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Constrains
Basic module constrains
Code Block |
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language | ruby |
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title | _i_bitgen_common |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property CONFIG_VOLTAGE 1.8 [current_design]
set_property CFGBVS GND [current_design] |
Design specific constrain
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language | ruby |
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title | _i_timing.xdc |
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set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk0_clk_p]
set_false_path -from [get_clocks clk_fpga_0] -to [get_clocks si5338_clk3_clk_p]
set_false_path -from [get_clocks si5338_clk0_clk_p] -to [get_clocks clk_fpga_0]
set_false_path -from [get_clocks si5338_clk3_clk_p] -to [get_clocks clk_fpga_0] |
Software Design - Vitis
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For Vitis project creation, follow instructions from:
Vitis
Application
follow instructions from:
Vitis
Application
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---------------------------------------------------------- FPGA Example |
----------------------------------------------------------FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20192023.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 2019.2 xilisf_v5_11 Changed default Flash type to 5.2023.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: ----------------------------------------------------------Zynq Example: zynq_fsblTE modified 20192023.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2019.2 FSBL General: Modified Files: main.cGeneral Changes: Display FSBL BannerSet FSBL Boot Mode to JTAGDisable Memory initialisation
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20192023.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2019.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIODisable Memory initialisation
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. Vitis Vitis is used to generate Boot.bin. |
Template location: "<project folder>\sw_lib\sw_apps\"fsbl
TE modified 20212023.2 FSBL
General:
Module Specific:
- Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+USB Reset over MIO
hello_te0745
Hello TE0745 is a Xilinx Hello World example as endless loop instead of one console output.
u-boot
U-Boot.elf is generated with PetaLinux. Vitis is used to generate Boot.bin.
Software Design - PetaLinux
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For PetaLinux installation and project creation, follow instructions from:
Config
Start with petalinux-config or petalinux-config --get-hw-description
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_SUBSYSTEM_ETHERNET_PS7_ETHERNET_0_MAC=""
- add new flash partition for bootscr and sizing
- CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART0_SIZE=0xA00000
- CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART2PART1_SIZE=0x1400000
- CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_NAME="bootscr"
- CONFIG_SUBSYSTEM_FLASH_PS7_QSPI_0_BANKLESS_PART3_SIZE=0x40000
- Identification
- CONFIG_SUBSYSTEM_HOSTNAME="Trenz"
- CONFIG_SUBSYSTEM_PRODUCT="TE0745_TEB0745"
U-Boot
Start with petalinux-config -c u-boot
Changes:
- MAC from eeprom together with uboot and device tree settings:
- CONFIG_ENV_OVERWRITE=y
- CONFIG_NVMEM=y
- CONFIG_DM_RTC=y (needed for nvmem driver because of bug in uboot)
- Boot Modes:
- CONFIG_QSPI_BOOT=y
- CONFIG_SD_BOOT=y
- CONFIG_ENV_IS_IN_FAT is not set
- # CONFIG_ENV_IS_IN_NAND is not set
- CONFIG_ENV_IS_IN_SPI_FLASH is not set
- CONFIG_BOOT_SCRIPT_OFFSET=0x1E20000
- Identification
- CONFIG_IDENT_STRING=" TE0745_TEB0745"
Change platform-top.h:
Code Block |
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#include <configs/zynq-common.h>
#no changes |
Device Tree
Code Block |
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language | js |
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title | project-spec\meta-user\recipes-bsp\device-tree\files\system-user.dtsi |
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/include/ "system-conf.dtsi"
/*--------------------------- QSPI -----------------------*/
&qspi {
#address-cells = <1>;
#size-cells = <0>;
status = "okay";
flash0: flash@0 {
compatible = "jedec,spi-nor";
reg = <0x0>;
#address-cells = <1>;
#size-cells = <1>;
spi-rx-bus-width #address-cells= <4>;
spi-tx-bus-width = <1>;
#size-cells<4>;
spi-max-frequency = <1><90000000>;
};
};
/*-------------------------- ETH PHY ---------------------*/
&gem0 {
phy-handle = <&phy0>;
nvmem-cells = <ð0_addr>;
nvmem-cell-names = "mac-address";
//required otherwise petalinux gives a static MAC address, this can also be achieved by setting petalinux CONFIG_SUBSYSTEM_ETHERNET_[XXXX]_MAC to
an empty nvmem-cells = <ð0_addr>;
nvmem-cell-names = "string
/delete-property/ local-mac-address";
mdio {
#address-cells = <1>;
#size-cells = <0>;
phy0: phy@1 {
compatible = "marvell,88e1510";
device_type = "ethernet-phy";
reg = <1>;
} ;
} ;
};
/*---------------------------- USB ----------------------*/
/{
usb_phy0: usb_phy@0 {
compatible = "ulpi-phy";
#phy-cells = <0>;
reg = <0xe0002000 0x1000>;
view-port = <0x0170>;
drv-vbus;
};
};
&usb0 {
dr_mode = "host";
//dr_mode = "peripheral";
usb-phy = <&usb_phy0>;
};
/*---------------------------- I2C -----------------------*/
&i2c0 {
rtc@6F {
compatible = "isil,isl12022";
reg = <0x6F>;
};
//MAC EEPROM
eeprom: eeprom@53 {
compatible = "microchip,24aa025", "atmel,24c02";
reg = <0x53>;
#address-cells = <1>;
#size-cells = <1>;
eth0_addr: eth-mac-addr@FA {
reg = <0xFA 0x06>;
};
};
i2cmux_SFP: i2cmux@72 {
compatible = "nxp,pca9548";
reg = <0x72>;
SFP@0 {
#address-cells = <1>;
#size-cells = <0>;
reg = <0>;
};
SFP@1 {
#address-cells = <1>;
#size-cells = <0>;
reg = <1>;
};
SFP@2 {
#address-cells = <1>;
#size-cells = <0>;
reg = <2>;
};
SFP@3 {
#address-cells = <1>;
#size-cells = <0>;
reg = <3>;
};
SFP@4 {
#address-cells = <1>;
#size-cells = <0>;
reg = <4>;
};
SFP@5 {
#address-cells = <1>;
#size-cells = <0>;
reg = <5>;
};
SFP@6 {
#address-cells = <1>;
#size-cells = <0>;
reg = <6>;
};
SFP@7 {
#address-cells = <1>;
#size-cells = <0>;
reg = <7>;
};
};
};
|
Kernel
Start with petalinux-config -c kernel
Changes:
- for Real Time Clock ISL12020MIRZ
- CONFIG_RTC_DRV_ISL12022=y
Rootfs
Start with petalinux-config -c rootfs
Changes:
- For web server app:
- For additional test tools only:
- CONFIG_i2c-tools=y
- CONFIG_packagegroup-petalinux-utils=y (util-linux,cpufrequtils,bridge-utils,mtd-utils,usbutils,pciutils,canutils,i2c-tools,smartmontools,e2fsprogs)
- For auto login:
- CONFIG_imagefeature-serial-autologin-root=y
FSBL patch (alternative for vitis fsbl trenz patch)
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-bsp\embeddedsw"
Petalinux Troubleshoot#Petalinux2023.2
Applications
See "<project folder>\os\petalinux\project-spec\meta-user\recipes-apps\"
startup
Script App to load init.sh from SD Card if available.
webfwu
Webserver application suitable for Zynq access. Need busybox-httpd
Additional Software
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Page properties |
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
|
SI5338
File location "<project folder>\misc\PLL\Si5338_B\Si5338-*.slabtimeproj"
General documentation how you work with this project will be available on Si5338
Appx. A: Change History and Legal Notices
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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Document Change History
To get content of older revision go to "Change History" of this page and select older document revision number.
Page properties |
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- Note this list must be only updated, if the document is online on public doc!
- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Scroll Title |
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anchor | Table_dch |
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title-alignment | center |
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title | Document change history. |
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Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
---|
repeatTableHeaders | default |
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style | |
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widths | 2*,*,3*,4* |
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sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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|
Date | Document Revision | Authors | Description |
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Page info |
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| modified-date |
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| modified-date |
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dateFormat | yyyy-MM-dd |
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| Page info |
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infoType | Current version |
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dateFormat | yyyy-MM-dd |
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prefix | v. |
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type | Flat |
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| Page info |
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infoType | Modified by |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| - Release 2023.2
- new assembly variants
| 2023-04-25 | v.15 | Manuela Strücker | | 2023-02-08 | v.14 | Manuela Strücker
| - Release 2021.2
- new assembly variants
- added jtag2axi for test purposes
| 2020-03-30 | v.13 | John Hartfiel | | 2019-09-18 | v.12 | John Hartfiel | - bugfix for TE0745-02-45-3EA
| 2018-12-19 | v.11 | John Hartfiel | | | v.10 | John Hartfiel | - update 2018.2
- documentation style update
| | v.7 | John Hartfiel | | 2018-02-09 | v.6 | John Hartfiel | | 2017-09-11 | v.1 | John Hartfiel | | -- | all | Page info |
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infoType | Modified users |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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| -- |
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Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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|