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Power Rail Name on B2B Connector | J1 Pins | J2 Pins | J3 Pins | Direction | Notes |
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VIN | - | 165, 166, 167, 168 | - | Input | external power supply voltage |
C3.3V | - | 147, 148 | - | Input | Normally leave unconnected |
3.3V | - | 111, 112, 123, 124, 135 136 169, 170, 171, 172 | - | Output | internal 3.3V voltage level |
1.8V | 169, 170, 171, 172 | - | - | Output | internal 1.8V voltage level |
EXT_IO_VCC | 99, 100 | - | - | Input | SC CPLD bank 1, 2 and 4 voltage |
VCCIO_10 | - | - | 99, 100 | Input | high range I/O bank voltage |
VCCIO_11 | - | - | 159, 160 | Input | high range I/O bank voltage |
VCCIO_12 | - | 159, 160 | - | Input | high range I/O bank voltage |
VCCIO_13 | - | 99, 100 | - | Input | high range I/O bank voltage |
VBAT_IN | - | - | 124 | Input | backup battery voltage |
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Parameter | Min | Max | Units | Notes |
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VIN supply voltage | -0.3 | 15 | V | LTM4644 datasheet |
VBAT supply voltage | -0.3 | 6 | V | TPS780180 datasheet |
PS I/O supply voltage, VCCO_PSIO | -0.5 | 3.6 | V | Xilinx document DS191 |
PS I/O input voltage | -0.4 | VCCO_PSIO + 0.55 | V | Xilinx document DS191 |
HP I/O bank supply voltage, VCCO | -0.5 | 2.0 | V | Xilinx document DS191 |
HP I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS191 |
HR I/O bank supply voltage, VCCO | -0.5 | 3.6 | V | Xilinx document DS191 |
HR I/O bank input voltage | -0.55 | VCCO + 0.55 | V | Xilinx document DS191 |
Differential input voltage | -0.4 | 2.625 | V | Xilinx document DS191 |
MGT reference clocks absolute input voltage | -0.5 | 1.32 | V | Xilinx document DS191 |
MGT absolute input voltage | -0.5 | 1.26 | V | Xilinx document DS191 |
Voltage on SC CPLD pins | -0.5 | 3.75 | V | Lattice Semiconductor MachXO2 datasheet |
Storage temperature | -40 | +85 | °C | See eMMC MTFC4GMVEA eMMC MTFC4GACAJCN datasheet |
Table 18: Module absolute maximum ratings
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Date | Revision | Contributors | Description | ||||||||||||||||||||||||||
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2018-08-07 | v.18 | Ali Naseri |
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Table 21: Document change history
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