Page properties |
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Template Revision 3.1 Design Name is always "TE Series Name" + Design name, for example "TE0720 Test Board" - Change List 3.0 to 3.1
- Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
- Change List 2.9 to 3.0
- add fix table of content
- add table size as macro
- removed page initial creator
|
Page properties |
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|
Important General Note:
Export PDF to download, if vivado revision is changed!
Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro
Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)Figure template (note: inner scroll ignore/only only with drawIO object):
Scroll Title |
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anchor | Figure_xyz |
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title | Text |
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|
Scroll Ignore |
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Create DrawIO object here: Attention if you copy from other page, use |
Scroll Only |
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image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed |
Date | Version | Changes | Author |
---|
2023-06-13 | 3.1.16 | - Design flow:
- added alternative programming files in Petalinux
- added chapter FSBL Patch in Software Design - Petalinux
| ma | 2023-06-01 | 3.1.15 | - removed u-boot.dtb from Design flow
| ma | 2023-06-01 | 3.1.14 | - expandable lists for revision history and supported hardware
| wh | 2023-05-25 | 3.1.13 | - updated according to Vivado 2022.2
| ma | 2023-02-08 | 3.1.12 | - removed content of
- Special FSBL for QSPI programming
| ma | 2022-08-24 | 3.1.11 | - Modification from link "available short link"
| ma | 2022-01-25 | 3.1.10 | - removed u-boot.dtb from QSPI-Boot mode and SD-Boot mode. Is implemented in BOOT.bin
- corrected Boot Source File in Boot Script-File
| ma | 2022-01-14 | 3.1.9 | - extended notes for microblaze boot process with linux
- add u.boot.dtb to petalinux notes
- add dtb to prebuilt content
- replace 20.2 with 21.2
| jh | 2021-06-28 | 3.1.8 | - added boot process for Microblaze
- minor typos, formatting
| ma | 2021-06-01 | 3.1.7 | | jh | 2021-05-04 | 3.1.6 | - removed zynq_ from zynq_fsbl
| ma | 2021-04-28 | 3.1.5 | - added macro "Scroll ignore" for suppression of horizontal dividing lines during .pdf-export
- minor typos, formatting
| ma | 2021-04-27 | 3.1.4 | - Version History
- changed from list to table
- Design flow
- removed step 5 from Design flow
- changed link from TE Board Part Files to Vivado Board Part Flow
- changed cmd shell from picture to codeblock
- added hidden template for "Copy PetaLinux build image files", depending from hardware
- added hidden template for "Power on PCB", depending from hardware
- Usage update of boot process
- Requirements - Hardware
- added "*used as reference" for hardware requirements
- all
- placed a horizontal separation line under each chapter heading
- changed title-alignment for tables from left to center
- all tables
- added "<project folder>\board_files" in Vivado design sources
| ma |
| 3.1.3 | | ma |
| 3.1.2 | - minor typing corrections
- replaced SDK by Vitis
- changed from / to \ for windows paths
- replaced <design name> by <project folder>
- added "" for path names
- added boot.src description
- added USB for programming
| ma |
| 3.1.1 | - swapped order from prebuilt files
- minor typing corrections
- removed Win OS path length from Design flow, added as caution in Design flow
| ma |
| 3.1 | - Fix problem with pdf export and side scroll bar
- update 19.2 to 20.2
- add prebuilt content option
|
|
| 3.0 | - add fix table of content
- add table size as macro
- removed page initial creator
|
|
|
Page properties |
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|
Important General Note: Export PDF to download, if vivado revision is changed! Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro - Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)
- ...
|
Overview
Scroll Ignore |
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scroll-pdf | true |
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scroll-office | true |
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scroll-chm | true |
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scroll-docbook | true |
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scroll-eclipsehelp | true |
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scroll-epub | true |
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scroll-html | true |
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|
Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via Vitis.Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.
Key Features
Page properties |
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Notes : - Add basic key futures, which can be tested with the design
|
Excerpt |
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- Vitis/Vivado 2022.2
- QSPI
- Custom Carrier (minimum PS Design with available module components only)
- Modified FSBL (some additional outputs only)
|
Revision History
Page properties |
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Notes : - add every update file on the download
- add design changes on description
|
Expand |
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|
Scroll Title |
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anchor | Table_DRH |
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title-alignment | center |
---|
title | Design Revision History |
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| |
|
Table template:
- Layout macro can be use for landscape of large tables
- Set column width manually(can be used for small tables to fit over whole page) or leave empty (automatically)
Scroll Title |
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|
Scroll Table Layout |
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orientation | portrait |
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sortDirection | ASC |
---|
repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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sortEnabled | false |
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cellHighlighting | true |
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Example | Comment |
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1 | 2 |
...Overview
Design Example with minimum PS Setup (DDR, QSPI, UART0) only for custom boards or easier debug via SDK.
Refer to http://trenz.org/te0807-info for the current online version of this manual and other available documentation.
Key Features
Page properties |
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|
Notes : - Add basic key futures, which can be tested with the design
|
Excerpt |
---|
- Vitis/Vivado 2020.2
- QSPI
- Custom Carrier (minimum PS Design with available module components only)
- Modified FSBL (some additional outputs only)
- Special FSBL for QSPI Programming
|
Revision History
Page properties |
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|
Notes : - add every update file on the download
- add design changes on description
|
Scroll Title |
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anchor | Table_DRH |
---|
title | Design Revision History |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Date | Vivado | Project Built | Authors | Description |
---|
2021-02-08 | 2020.2 | TE0807-test_board_noprebuilt-vivado_2020.2-build_1_20210208093457.zip TE0807-test_board-vivado_2020.2-build_1_20210208093443.zip | John Hartfiel | |
2020-10-06 | 2019.2 | TE0807-test_board_noprebuilt-vivado_2019.2-build_15_20201006121447.zip TE0807-test_board-vivado_2019.2-build_15_20201006121342.zip | John Hartfiel | |
2020-03-25 | 2019.2 | TE0807-test_board_noprebuilt-vivado_2019.2-build_8_20200325082749.zip TE0807-test_board-vivado_2019.2-build_8_20200325082730.zip | John Hartfiel | |
2020-01-27 | 2019.2 | TE0807-test_board_noprebuilt-vivado_2019.2-build_4_20200127075704.zip TE0807-test_board-vivado_2019.2-build_4_20200127075454.zip | John Hartfiel | - 2019.2 update
- Vitis support
|
2019-05-22 | 2018.3 | TE0807-test_board_noprebuilt-vivado_2018.3-build_05_20190522132408.zip TE0807-test_board-vivado_2018.3-build_05_20190522132356.zip | John Hartfiel | - custom FSBL
- Note: Prebuilt for ES2 version not included
|
2019-02-08 | 2018.2 | TE0807-test_board_noprebuilt-vivado_2018.2-build_04_20190207111539.zip TE0807-test_board-vivado_2018.2-build_04_20190207111524.zip | John Hartfiel | |
2018-09-04 | 2018.2 | TE0807-test_board_noprebuilt-vivado_2018.2-build_03_20180904121458.zip TE0807-test_board-vivado_2018.2-build_03_20180904121522.zip | John Hartfiel | - additional notes for FSBL generated with Win SDK
- changed *.bif
|
2018-01-18 | 2017.4 | TE0807-test_board_noprebuilt-vivado_2017.4-build_05_20180118152119.zip TE0807-test_board-vivado_2017.4-build_05_20180118152104.zip | John Hartfiel | |
| 2017.2 | TE0807-test_board_noprebuilt-vivado_2017.2-build_05_20171114115524.zip TE0807-test_board-vivado_2017.2-build_05_20171114115511.zip | John Hartfiel | |
Release Notes and Know Issues
Page properties |
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|
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
|
Scroll Title |
---|
anchor | Table_KI |
---|
title | Known Issues |
---|
|
scroll-tablelayout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
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widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
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cellHighlighting | true |
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|
| IssuesDescription | Workaround | To be fixed version |
---|
No known issues | --- | --- | --- |
Requirements
Software
Page properties |
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|
Notes : - list of software which was used to generate the design
|
Scroll Title |
---|
anchor | Table_SW |
---|
title | Software |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Software | Version | Note |
---|
Vitis | 2020.2 | needed, Vivado is included into Vitis installation |
Hardware
Page properties |
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|
Notes : - list of software which was used to generate the design
|
Basic description of TE Board Part Files is available on TE Board Part Files.
Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Scroll Title |
---|
anchor | Table_HWM |
---|
title | Hardware Modules |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|
TE0807-01-07EV-ES | es2_2gb | REV01 | 2GB | 64GB | NA | NA | Not longer supported by vivado |
TE0807-02-07EV-1E | 7ev_1e_4gb | REV02 | 4GB | 64GB | NA | NA | NA |
TE0807-02-07EV-1EK | 7ev_1e_4gb | REV02 | 4GB | 64GB | NA | NA | with heat sink |
TE0807-02-4BE21-A | 4eg_1e_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7DE21-A | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7DI21-C | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | without encryption |
TE0807-02-7DI21-A | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-4AI21-A | 4cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-5AI21-A | 5cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7AI21-A | 7cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7DI24-A | 7ev_1i_4gb | REV02 | 4GB | 512MB | NA | NA | NA |
TE0807-02-7DE21-AK | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink |
TE0807-02-4AI21-X | 4cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | U41 replaced with diode |
TE0807-02-4BE21-AK | 4eg_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink |
TE0807-02-7DI21-AK | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink |
TE0807-02-5DI21-A | 5ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-02-7NE21-A | 7ev_3e_4gb | REV02 | 4GB | 128MB | NA | NA | NA |
TE0807-03-5DI21-A | 5ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7NE21-A | 7ev_3e_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-4AI21-X | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | U41 replaced with diode |
TE0807-03-4AI21-A | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-4AI21-C | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | without encryption |
TE0807-03-4BE21-A | 4eg_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-5AI21-A | 5cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7AI21-A | 7cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7DE21-A | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7DE21-AK | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | with heat sink |
TE0807-03-7DI21-A | 7ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA |
TE0807-03-7DI21-C | 7ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | without encryption |
TE0807-03-7DI24-A | 7ev_1i_4gb | REV03 | 4GB | 512MB | NA | NA | NA |
Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this boart part files are not used for this reference design.
Design supports following carriers:
Scroll Title |
---|
anchor | Table_HWC |
---|
title | Hardware Carrier |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Carrier Model | Notes |
---|
Custom PCB | use simple Board Part files, if MIO connected is different to TEBF0808 |
TEBF0808 | Used as reference carrier. |
TEBT0808-01 | Change UART0 to UART1 (MIO68...69) and regenerate design |
Additional HW Requirements:
Scroll Title |
---|
anchor | Table_AHW |
---|
title | Additional Hardware |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Additional Hardware | Notes |
---|
--- | --- |
Content
For general structure and of the reference design, see Project Delivery - Xilinx devices
Design Sources
Scroll Title |
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anchor | Table_DS |
---|
title | Design sources |
---|
|
Scroll Table Layout |
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orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | widths | sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
Type | Location | Notes |
---|
Vivado | <design name>/block_design <design name>/constraints <design name>/ip_lib | Vivado Project will be generated by TE Scripts |
Vitis | <design name>/sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
Project Built | Authors | Description |
---|
2023-08-17 | 2022.2 | TE0807-test_board-vivado_2022.2-build_6_20230817092607.zip TE0807-test_board_noprebuilt-vivado_2022.2-build_6_20230817092607.zip | Manuela Strücker | - 2022.2 update
- new assembly variants
| 2022-10-17 | 2021.2.1 | TE0807-test_board_noprebuilt-vivado_2021.2-build_18_20221017093249.zip TE0807-test_board-vivado_2021.2-build_18_20221017093249.zip | Manuela Strücker | | 2022-09-12 | 2021.2.1 | TE0807-test_board_noprebuilt-vivado_2021.2-build_15_20220912085423.zip TE0807-test_board-vivado_2021.2-build_15_20220912085423.zip | Manuela Strücker | - update board part file compatible to Vivado 2021.2.1
| 2022-05-18 | 2021.2 | TE0807-test_board_noprebuilt-vivado_2021.2-build_14_20220518130935.zip TE0807-test_board-vivado_2021.2-build_14_20220518130935.zip | Manuela Strücker | - 2021.2 update
- new assembly variants
- update document style
| 2021-02-08 | 2020.2 | TE0807-test_board_noprebuilt-vivado_2020.2-build_1_20210208093457.zip TE0807-test_board-vivado_2020.2-build_1_20210208093443.zip | John Hartfiel | | 2020-10-06 | 2019.2 | TE0807-test_board_noprebuilt-vivado_2019.2-build_15_20201006121447.zip TE0807-test_board-vivado_2019.2-build_15_20201006121342.zip | John Hartfiel | | 2020-03-25 | 2019.2 | TE0807-test_board_noprebuilt-vivado_2019.2-build_8_20200325082749.zip TE0807-test_board-vivado_2019.2-build_8_20200325082730.zip | John Hartfiel | | 2020-01-27 | 2019.2 | TE0807-test_board_noprebuilt-vivado_2019.2-build_4_20200127075704.zip TE0807-test_board-vivado_2019.2-build_4_20200127075454.zip | John Hartfiel | - 2019.2 update
- Vitis support
| 2019-05-22 | 2018.3 | TE0807-test_board_noprebuilt-vivado_2018.3-build_05_20190522132408.zip TE0807-test_board-vivado_2018.3-build_05_20190522132356.zip | John Hartfiel | - custom FSBL
- Note: Prebuilt for ES2 version not included
| 2019-02-08 | 2018.2 | TE0807-test_board_noprebuilt-vivado_2018.2-build_04_20190207111539.zip TE0807-test_board-vivado_2018.2-build_04_20190207111524.zip | John Hartfiel | | 2018-09-04 | 2018.2 | TE0807-test_board_noprebuilt-vivado_2018.2-build_03_20180904121458.zip TE0807-test_board-vivado_2018.2-build_03_20180904121522.zip | John Hartfiel | - additional notes for FSBL generated with Win SDK
- changed *.bif
| 2018-01-18 | 2017.4 | TE0807-test_board_noprebuilt-vivado_2017.4-build_05_20180118152119.zip TE0807-test_board-vivado_2017.4-build_05_20180118152104.zip | John Hartfiel | | | 2017.2 | TE0807-test_board_noprebuilt-vivado_2017.2-build_05_20171114115524.zip TE0807-test_board-vivado_2017.2-build_05_20171114115511.zip | John Hartfiel | |
|
|
Release Notes and Know Issues
Page properties |
---|
|
Notes :- add known Design issues and general notes for the current revision
- do not delete known issue, add fixed version time stamp if issue fixed
|
Scroll Title |
---|
anchor | Table_KI |
---|
title-alignment | center |
---|
title | Known Issues |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Issues | Description | Workaround | To be fixed version |
---|
Xilinx Software | Incompatibility of board files for ZynqMP with eMMC activated between 2021.2 and 2021.2.1 patch, see Xilinx Forum Request | use corresponding board files for the Vivado versions | -- | QSPI Flash | Flash programming is not supported with boot mode QSPI or SD.
| If flash programming fails, configure device for JTAG boot mode and try again or use older Vivado Versions for programming. (Vivado 2020.2 or 2019.2)
| -- |
|
Requirements
Software
Page properties |
---|
|
Notes : - list of software which was used to generate the design
|
Scroll Title |
---|
anchor | Table_SW |
---|
title-alignment | center |
---|
title | Software |
---|
|
Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Software | Version | Note |
---|
Vitis | 2022.2 | needed, Vivado is included into Vitis installation |
|
Hardware
Page properties |
---|
|
Notes : - list of hardware which was used to generate the design
- mark the module and carrier board, which was used tested with an *
|
Basic description of TE Board Part Files is available on TE Board Part Files.Complete List is available on <design name>/board_files/*_board_files.csv
Design supports following modules:
Expand |
---|
|
Scroll Title |
---|
anchor | Table_HWM |
---|
title-alignment | center |
---|
title | Hardware Modules |
---|
| Scroll Table Layout |
---|
orientation | portrait |
---|
sortDirection | ASC |
---|
repeatTableHeaders | default |
---|
style | |
---|
widths | |
---|
sortByColumn | 1 |
---|
sortEnabled | false |
---|
cellHighlighting | true |
---|
|
Module Model | Board Part Short Name | PCB Revision Support | DDR | QSPI Flash | EMMC | Others | Notes |
---|
TE0807-01-07EV-ES | es2_2gb | REV01 | 2GB | 64GB | NA | NA | Not longer supported by vivado | TE0807-02-07EV-1E | 7ev_1e_4gb | REV02 | 4GB | 64GB | NA | NA | NA | TE0807-02-07EV-1EK | 7ev_1e_4gb | REV02 | 4GB | 64GB | NA | NA | with heat sink | TE0807-02-4BE21-A | 4eg_1e_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-7DE21-A | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-7DI21-C | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | without encryption | TE0807-02-7DI21-A | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-4AI21-A | 4cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-5AI21-A | 5cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-7AI21-A | 7cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-7DI24-A | 7ev_1i_4gb | REV02 | 4GB | 512MB | NA | NA | NA | TE0807-02-7DE21-AK | 7ev_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink | TE0807-02-4AI21-X | 4cg_1i_4gb | REV02 | 4GB | 128MB | NA | NA | U41 replaced with diode | TE0807-02-4BE21-AK | 4eg_1e_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink | TE0807-02-7DI21-AK | 7ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | with heat sink | TE0807-02-5DI21-A | 5ev_1i_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-02-7NE21-A | 7ev_3e_4gb | REV02 | 4GB | 128MB | NA | NA | NA | TE0807-03-5DI21-A | 5ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7NE21-A | 7ev_3e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-4AI21-X | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | U41 replaced with diode | TE0807-03-4AI21-A | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-4AI21-C | 4cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | without encryption | TE0807-03-4BE21-A | 4eg_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-5AI21-A | 5cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7AI21-A | 7cg_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7DE21-A* | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7DE21-AK | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | with heat sink | TE0807-03-7DI21-A | 7ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7DI21-C | 7ev_1i_4gb | REV03 | 4GB | 128MB | NA | NA | without encryption | TE0807-03-7DI24-A | 7ev_1i_4gb | REV03 | 4GB | 512MB | NA | NA | NA | TE0807-03-4BE21-AK | 4eg_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-S004 | 7ev_1e_me_8gb | REV03 | 8GB | 128MB | NA | NA | CAO | TE0807-03-S005 | 7ev_1i_4gb | REV03 | 4GB | 512MB | NA | NA | CAO | TE0807-03-S008 | 7ev_1i_me_8gb | REV03 | 8GB | 128MB | NA | without PLL | CAO Micron DDR | TE0807-03-S014 | 4eg_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-7DE21-AZ | 7ev_1e_4gb | REV03 | 4GB | 128MB | NA | NA | NA | TE0807-03-S011 | 7ev_1i_me_8gb | REV03 | 8GB | 128MB | NA | without PLL | CAO Micron DDR |
*used as reference |
|
Note: Design contains also Board Part Files for TE0807+TEBF0808 configuration, this board part files are not used for this reference design.
Design supports following carriers:
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Carrier Model | Notes |
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Custom PCB | use simple Board Part files, if MIO connected is different to TEBF0808 | TEBF0808* | Used as reference carrier. | TEBT0808-01 | Change UART0 to UART1 (MIO68...69) and regenerate design |
*used as reference |
Additional HW Requirements:
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--- | --- |
*used as reference |
Content
For general structure and usage of the reference design, see Project Delivery - AMD devices
Design Sources
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Type | Location | Notes |
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Vivado | <project folder>\block_design <project folder>\constraints <project folder>\ip_lib <project folder>\board_files | Vivado Project will be generated by TE Scripts | Vitis | <project folder>\sw_lib | Additional Software Template for Vitis and apps_list.csv with settings automatically for Vitis app generation |
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Additional Sources
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Type | Location | Notes |
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--- | --- | --- |
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Prebuilt
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Notes : - prebuilt files
- Template Table:
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | Boot Script-File | *.scr | Distro Boot Script file | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Debian SD-Image | *.img | Debian Image for SD-Card | Diverse Reports | --- | Report files in different formats | Device Tree | *.dts | Device tree (2 possible, one for u-boot and one for linux) | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) | MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) | OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems | SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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title | Prebuilt files (only on ZIP with prebult content) |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File | BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) | BIT-File | *.bit | FPGA (PL Part) Configuration File | DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface | Diverse Reports | --- | Report files in different formats | Hardware-Platform-Description-File | *.xsa | Exported Vivado hardware description file for Vitis and PetaLinux | LabTools Project-File | *.lpr | Vivado Labtools Project File | Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
|
Download
Reference Design is only usable with the specified Vivado/Vitis/PetaLinux version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:Design Flow
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Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/Vitis GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
Note |
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Caution! Win OS has a 260 character limit for path lengths which can affect the Vivado tools. To avoid this issue, use Virtual Drive or the shortest possible names and directory locations for the reference design (for example "x:\<project folder>") |
Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
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language | bash |
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theme | Midnight |
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title | _create_win_setup.cmd/_create_linux_setup.sh |
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------------------------Set design paths----------------------------
-- Run Design with: _create_win_setup
-- Use Design Path: <absolute project path>
--------------------------------------------------------------------
-------------------------TE Reference Design---------------------------
--------------------------------------------------------------------
-- (0) Module selection guide, project creation...prebuilt export...
-- (1) Create minimum setup of CMD-Files and exit Batch
-- (2) Create maximum setup of CMD-Files and exit Batch
-- (3) (internal only) Dev
-- (4) (internal only) Prod
-- (c) Go to CMD-File Generation (Manual setup)
-- (d) Go to Documentation (Web Documentation)
-- (g) Install Board Files from Xilinx Board Store (beta)
-- (a) Start design with unsupported Vivado Version (beta)
-- (x) Exit Batch (nothing is done!)
----
Select (ex.:'0' for module selection guide): |
- Press 0 and enter to start "Module Selection Guide"
- Createproject and follow instructions of the product selection guide, settings file will be configured automatically during this process.
Additional Sources
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title | Additional design sources |
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Type | Location | Notes |
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--- | --- | --- |
Prebuilt
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Notes :
prebuilt filesTemplate Table: Scroll Title |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Boot Source | *.scr | Distro Boot file |
DebugProbes-File | *.ltx | Definition File for Vivado/Vivado Labtools Debugging Interface |
Debian SD-Image | *.img | Debian Image for SD-Card |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
MCS-File | *.mcs | Flash Configuration File with Boot-Image (MicroBlaze or FPGA part only) |
MMI-File | *.mmi | File with BRAM-Location to generate MCS or BIT-File with *.elf content (MicroBlaze only) |
OS-Image | *.ub | Image with Linux Kernel (On Petalinux optional with Devicetree and RAM-Disk) |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
SREC-File | *.srec | Converted Software Application for MicroBlaze Processor Systems |
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anchor | Table_PF |
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title | Prebuilt files (only on ZIP with prebult content) |
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repeatTableHeaders | default |
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style | widths | sortByColumn | 1 |
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File | File-Extension | Description |
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BIF-File | *.bif | File with description to generate Bin-File |
BIN-File | *.bin | Flash Configuration File with Boot-Image (Zynq-FPGAs) |
BIT-File | *.bit | FPGA (PL Part) Configuration File |
Diverse Reports | --- | Report files in different formats |
Hardware-Platform-Specification-Files | *.xsa | Exported Vivado Hardware Specification for Vitis and PetaLinux |
LabTools Project-File | *.lpr | Vivado Labtools Project File |
Software-Application-File | *.elf | Software Application for Zynq or MicroBlaze Processor Systems |
Download
Reference Design is only usable with the specified Vivado/SDK/PetaLinux/SDx version. Do never use different Versions of Xilinx Software for the same Project.
Reference Design is available on:
Design Flow
Note |
---|
Reference Design is available with and without prebuilt files. It's recommended to use TE prebuilt files for first lunch. |
Trenz Electronic provides a tcl based built environment based on Xilinx Design Flow.
See also:
The Trenz Electronic FPGA Reference Designs are TCL-script based project. Command files for execution will be generated with "_create_win_setup.cmd" on Windows OS and "_create_linux_setup.sh" on Linux OS.
TE Scripts are only needed to generate the vivado project, all other additional steps are optional and can also executed by Xilinx Vivado/SDK GUI. For currently Scripts limitations on Win and Linux OS see: Project Delivery Currently limitations of functionality
- _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell:
Image Removed - Press 0 and enter to start "Module Selection Guide"
- (optional Win OS) Generate Virtual Drive or use short directory for the reference design (for example x:\<design name>)
- Create Project (follow instruction of the product selection guide), settings file will be configured automatically during this process
(optional for manual changes) TE FilesFlow Important: Use Board Part Files, which did not |
ends Create
XAS and hardware description file (.xsa file) and export to prebuilt folder
Run on Vivado TCL: Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates design and export files into "<project folder>\prebuilt\hardware\<short name>") |
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TE::hw_build_design -export_prebuilt |
Note: Script generate design and export files into \prebuilt\hardware\<short dir>. Use
Info |
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Using Vivado GUI is the same, except file export to prebuilt folder. |
Generate Programming Files with Vitis
Run on Vivado TCL: TE::sw_run_vitis -all
Note: Scripts generate Code Block |
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language | py |
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theme | Midnight |
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title | run on Vivado TCL (Script generates applications and bootable files, which are defined in "test_board\sw_lib\apps_list.csv") |
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(alternative) Start SDK with Vivado GUI or start with TE Scripts on Vivado TCL: TE::sw_run_vitis
Note: TE::sw_run_vitis -all
TE::sw_run_vitis (optional; Start Vitis from Vivado GUI or start with TE Scripts on Vivado TCL) |
Note |
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TCL scripts generate also platform project, this must be done |
manuelly manually in case GUI is used. See Vitis |
Launch
Programming Scroll Ignore |
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Note: - Programming and Startup procedure
|
Programming
Note |
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Check Module and Carrier TRMs for proper HW configuration before you try any designany design. Reference Design is also available with prebuilt files. It's recommended to use TE prebuilt files for first launch. |
Xilinx documentation for programming and debugging: Vivado/SDKVitis/SDSoC-Xilinx Software Programming and Debugging
Get prebuilt boot binaries
- Run _create_win_setup.cmd/_create_linux_setup.sh and follow instructions on shell
- Press 0 and enter to start "Module Selection Guide"
- Select assembly version
- Validate selection
Select
Create create and open delivery binary folder
( foler>/<Artikel ) () " for different applications will be generated |
QSPI-Boot mode
- Connect JTAG and power on carrier with module
Open Vivado Project with "vivado_open_existing_project_guimode.cmd" or if not created, create with "vivado_create_project_guimode.cmd"
Type Code Block |
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language | bash |
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theme | Midnight |
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title | run on Vivado TCL |
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Console: (Script programs BOOT.bin on QSPI flash) |
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TE::pr_program_flash |
_binfile Note: To program with SDK/Vivado GUI, use special FSBL (zynqmp_fsbl_flash) on setup
SD
SD-Boot mode
This does not work, because SD controller is not selected on PS.
JTAG
Load configuration and Application with Vitis Debugger into device.
Usage
QSPI Boot:
- Prepare HW like described on section 71631609 Programming
- Connect UART USB (most cases same as JTAG)
Select QSPI
Card as Boot Mode
Info |
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Note: See TRM of the Carrier, which is used. |
Power On PCB
Note: loads PMU Firmware and FSBL from QSPI into OCM, 2. FSBL loads Application into DDR
System Design - VivadoFSBL from QSPI into OCM, 2. FSBL init the PS, programs the PL using the bitstream and loads PMU, ATF and U-boot from QSPI into DDR |
System Design - Vivado
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Block Design
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anchor | Figure_BD |
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title-alignment | center |
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title | Block Design |
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PS Interfaces
Activated interfaces:
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anchor | Table_PSI |
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title-alignment | center |
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title | PS Interfaces |
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orientation | portrait |
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Type | Note |
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DDR |
| QSPI | MIO | UART0 | MIO, please select other one, if you have connected uart UART to second controller or other MIO | SWDT0..1 |
| TTC0..3 |
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Constrains
Basic module constrains
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language | ruby |
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title | _i_bitgen.xdc |
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set_property BITSTREAM.GENERAL.COMPRESS TRUE [current_design]
set_property BITSTREAM.CONFIG.UNUSEDPIN PULLNONE [current_design] |
Design specific constrain
Not needed.
Software Design - SDK/HSIDesign specific constrain
Not needed.
Software Design - Vitis
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For SDK Vitis project creation, follow instructions from:Vitis
Application
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---------------------------------------------------------- FPGA Example |
hidden | true |
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id | Comments----------------------------------------------------------FPGA Example scuMCS Firmware to configure SI5338 and Reset System. srec_spi_bootloaderTE modified 20202022.2 SREC Bootloader to load app or second bootloader from flash into DDR Descriptions: - Modified Files: blconfig.h, bootloader.c
- Changes:
- Add some console outputs and changed bootloader read address.
- Add bugfix for 2018.2 qspi flash
xilisf_v5_11TE modified 20202022.2 xilisf_v5_11 - Changed default Flash type to 5.
---------------------------------------------------------- Zynq Example: zynq_---------------------------------------------------------- fsblTE modified 20202022.2 FSBL General: Module Specific: - Add Files: all TE Files start with te_*
- READ MAC from EEPROM and make Address accessible by UBOOT (need copy defines on uboot uboot platform-top.h)
- CPLD access
- Read CPLD Firmware and SoC Type
- Configure Marvell PHY
zynq_fsbl_flashTE modified 2020.2 FSBL General: - Modified Files: main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
---------------------------------------------------------- ZynqMP Example: ---------------------------------------------------------- zynqmp_fsblTE modified 20202022.2 FSBL General: - Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
Module Specific: - Add Files: all TE Files start with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_fsbl_flashTE modified 2020.2 FSBL General: - Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.c
- General Changes:
- Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
- with te_*
- Si5338 Configuration
- ETH+OTG Reset over MIO
zynqmp_pmufwXilinx default PMU firmware. ---------------------------------------------------------- General Example:: ---------------------------------------------------------- hello_te0820Hello TE0820 is a Xilinx Hello World example as endless loop instead of one console output. u-bootU-Boot.elf is generated with PetaLinux. SDK/HSI Vitis is used to generate Boot.bin. |
Template location: ./"<project folder>\sw_lib/\sw_apps/\"zynqmp_fsbl
TE modified 20202022.2 FSBL
General:
- Modified Files: xfsbl_main.c, xfsbl_hooks.h/.c, xfsbl_board.h/.c (search for 'TE Mod' on source code)
- Add Files: te_xfsbl_hooks.h/.c (for hooks and board)\n\
- General Changes:
- Display FSBL Banner and Device Name
zynqmp_fsbl_flash
TE modified 2020.2 FSBL
General:
- Modified Files: xfsbl_initialisation.c, xfsbl_hw.h, xfsbl_handoff.c, xfsbl_main.cxfsbl_hooks.h/.c (for hooks and board)
- General Changes:
- Display Display FSBL Banner
- Set FSBL Boot Mode to JTAG
- Disable Memory initialisation
hello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Softwarehello_te0807
Hello TE0807 is a Xilinx Hello World example as endless loop instead of one console output.
Additional Software
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Note:
- Add description for other Software, for example SI CLK Builder ...
- SI5338 and SI5345 also Link to:
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No additional software is needed.
Appx. A: Change History and Legal Noticessoftware is needed.
Appx. A: Change History and Legal Notices
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Document Change History
To get content of older revision got revision go to "Change History" of this page and select older document revision number.
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- It's semi automatically, so do following
Add new row below first Copy "Page Information Macro (date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template - Metadata is only used of compatibility of older exports
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Date | Document Revision | Authors | Description |
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page-info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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| -info |
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infoType | Modified date |
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dateFormat | yyyy-MM-dd |
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type | Flat |
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infoType | Current version |
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prefix | v. |
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type | Flat |
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infoType | Modified by |
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type | Flat |
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| - 2022.2 update
- new assembly variants
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2022-10-17 | v.21 | Manuela Strücker | |
2022-09-12 | v.20 | Manuela Strücker | - update board part file compatible to Vivado 2021.2.1
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2022-09-06 | v.19 | Manuela Strücker | - 2021.2 update
- new assembly variants
- update document style
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2021-02-08 | v.15 | John Hartfiel Page info |
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infoType | Modified by |
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type | Flat- new assembly variants
- document style update
| 2020-10-06 | v.14 | John Hartfiel | |
2020-03-25 | v.13 | John Hartfiel | |
2020-01-27 | v.12 | John Hartfiel | - Release 2019.2
- new assembly variants
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2019-05-22 | v.10 | John Hartfiel | |
2019-02-07 | v.9 | John Hartfiel | |
| v.7 | John Hartfiel | |
2018-02-08 | v.5 | John Hartfiel | |
2017-11-14 | v.3 | John Hartfiel | |
-- | all | Page info |
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type | Flat |
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| -- |
Legal Notices
Include Page |
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| IN:Legal Notices |
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| IN:Legal Notices |
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