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Template Revision 3.1

  • Module: TRM Name always "TE Series Name" +TRM
    Example: "TE0728 TRM"

Template Change history:

  • Template Change history:

    • 3.02 to 3.1
      • New general notes for temperature range to "Recommended Operating Conditions"
    • 3.01 to 3.02
      • add again fix table of content with workaround to use it for pdf and wiki
      • Export Link for key features examples
        • Notes for different Types (with and without Main FPGA)
      • Export Link for Signals, Interfaces and Pins examples
        • Notes for different Types (Modul, Modul Hypride, Evalboard, Carrier)
    • 3.0 to 3.01
      • remove fix table of content and page layout ( split page layout make trouble with pdf export)
      • changed and add note to signal and interfaces, to on board periphery section
      • ...(not finished)
    • 2.13 to 3.00
      • → separation of Carrier/Module and evaluation kit TRM
    • 2.14 to 2.15
      • add excerpt macro to key features
    • 2.13 to 2.14
      • add fix table of content
      • add table size as macro


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Important General Note:

  • If some section is configurable and depends on Firmware, please refer to the addition page (for example CPLD). If not available, add note, that this part is configurable

  • Designate all graphics and pictures with a number and a description, Use "Scroll Title" macro

    • Use "Scroll Title" macro for pictures and table labels. Figure number must be set manually at the moment (automatically enumeration is planned by scrollPDF)

      • Figure template:

        Scroll Title
        anchorFigure_anchorname
        titleText


        Scroll Ignore

        Create DrawIO object here: Attention if you copy from other page, objects are only linked.


        Scroll Only

        image link to the generate DrawIO PNG file of this page. This is a workaround until scroll pdf export bug is fixed



      • Table template:

        • Layout macro can be use for landscape of large tables


      • Scroll Title
        anchorTable_tablename
        titleText

        Scroll Table Layout
        orientationportrait
        sortDirectionASC
        repeatTableHeadersdefault
        style
        widths
        sortByColumn1
        sortEnabledfalse
        cellHighlightingtrue

        ExampleComment
        12



    • The anchors of the Scroll Title should be named consistant across TRMs. A incomplete list of examples is given below

      • <type>_<main section>_<name>

        • type: Figure, Table
        • main section:
          • "OV" for Overview
          • "SIP" for Signal Interfaces and Pins,
          • "OBP" for On board Peripherals,
          • "PWR" for Power and Power-On Sequence,
          • "B2B" for Board to Board Connector,
          • "TS" for Technical Specification
          • "VCP" for Variants Currently in Production
          •  "RH" for Revision History
        • name: custom, some fix names, see below
      • Fix names:

        • "Figure_OV_BD" for Block Diagram

        • "Figure_OV_MC" for Main Components

        • "Table_OV_IDS" for Initial Delivery State

        • "Table_PWR_PC" for Power Consumption

        • "Figure_PWR_PD" for Power Distribution
        • "Figure_PWR_PS" for Power Sequence
        • "Figure_PWR_PM" for Power Monitoring
        • "Table_PWR_PR" for Power Rails
        • "Table_PWR_BV" for Bank Voltages

        • "Table_TS_AMR" for Absolute_Maximum_Ratings

        • "Table_TS_ROC" for Recommended_Operating_Conditions

        • "Figure_TS_PD" for Physical_Dimensions
        • "Table_VCP_SO" for TE_Shop_Overview

        • "Table_RH_HRH" for Hardware_Revision_History

        • "Figure_RH_HRN" for Hardware_Revision_Number
        • "Table_RH_DCH" for Document_Change_History
    • Use Anchor in the document: add link macro and add "#<anchorname>
    • Refer to Anchror from external : <page url>#<pagename without space characters>-<anchorname>



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-----------------------------------------------------------------------


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Note for Download Link of the Scroll ignore macro:


Scroll Ignore

Download PDF version of this document.

Overview

The Trenz Electronic TE0865  is an industrial/extended grade module based on Xilinx Zunq UltraScale+ MPSoC. The TE0865 is equipped with 4x 2GB DDR4 SDRAM connected to Programmable Logic(PL) and 5x 2GB DDR4 SDRAM connected to Processing System(PS), 8 GB eMMC, 2x 64MB Quad SPI Flash, Gigabit Ethernet Transceiver, USB Transceiver, Ultra micro power terminal and an Intel MAx 10 as system controller CPLD. TE0865 is a high-performance MPSoC module integrating a Xilinx Zynq UltraScale+ ZU17EG (other assembly options for the FPGA are available), up to 8 GByte DDR4 SDRAM with ECC on PS, up to 8 GByte DDR4 SDRAM on PL, 256 MByte Flash memory for configuration and operation, Gigabit Ethernet PHY, and powerful switch-mode power supplies for all on-board voltages. A large number of configurable I/O's is provided via rugged high-speed stacking connections. 

The prototype configuration of TE0865 will be available with many configuration options available that you can customize to meet your specific needs.

All parts are at least extended temperature range of 0°C to +85°C. The module operating temperature range depends on customer design and cooling solution. Please contact us for options.

Refer to http://trenz.org/te0865-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

→ See examples fro different types <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-KeyFeatures


Excerpt
  • SoC/FPGA
    • Package: C1760
    • Device: ZU11, ZU17, ZU19*
    • Engine: EG*
    • Speed: -1, -2,*, **
    • Temperature: I, E,*, **
  • RAM/Storage
    • Low Power DDR4 on PS with ECC
      • Data width: 16bit64 bit
      • Size: def. 2GB4GB*
      • Speed: 3200 2400 (MTGb/s) ***
      Low Power
    • DDR4 on PL
      • Data width: 16bit64 bit
      • Size: def. 2GB4GB*
      • Speed: max 2666 (Gb/s) ***
    •  eMMC
      • Data width: 8Bit8 Bit
      • size: def. 8GB 8 GB *
    • Dual QSPI boot Flash in dual parallel mode (size depends on assembly version)
      • Data width: 8bit
      • size: def. 64MB *
    • MAC address serial EEPROM with EUI-48™ node identity (Microchip 24AA025E48)
  • On Board
    • Intel Max 10 FPGA as CPLD
    • 6x MEMS Oscillator
    • Gigabit Ethernet transceiver PHY (Marvell Alaska 88E1512)
    • Hi-speed USB2 ULPI transceiver with full OTG support (Microchip USB3340C)
  • Interface
    • 214 x PS I/Os
    • 96x 96 HD I/Os
    • 416x 240 HP I/Os
    • 4x PS GTR
    • 3x Samtec Accelerate HD B2B connector
    • 78x 21 MIOs
  • Power
    • 12V input supply voltage
    • Variable Bank IO Power Input
  • Dimension
    • 7.5 cm x 10 cm
  • Notes
    • * depends on assembly version
    • ** also non low power assembly options possible
    • *** depends on used U+ Zynq and DDR4 combination

Block Diagram

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add drawIO object in Scroll Ignore section and add reference image in Scroll Only.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


Note

Title (not anchor) of all Scroll Title such as DrawIOs and Tables should be changed according to the Module name.

Example: TE0812 Block Diagram


Note

All created DrawIOs  should be named according to the Module name:

Example: DrawIO of TE0812 Block Diagram should be named TE0812_OV_BD



Scroll Title
anchorFigure_OV_BD
titleTE0865 block diagram


Scroll Ignore
Scroll Only
Image Removed
draw.io Diagram
borderfalse
diagramNameTE0865_OV_BD
simpleViewerfalse
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linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision35


Scroll Only

Image Added17


Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .



Scroll Title
anchorFigure_OV_MC
titleTE0865 main components


Scroll Ignore
draw.io Diagram
borderfalse
diagramNameTE0865_OV_MC
simpleViewerfalse
width
linksauto
tbstylehidden
diagramDisplayName
lboxtrue
diagramWidth641
revision413


Scroll Only


  1. ZYNQ Ultrascale+ MPSoC FPGA, U30
  2. PL DDR4 SDRAM, U9, U10, U28, U29
  3. PS DDR4 SDRAM, U5...U8, U11
  4. Intel MAX 10 FPGA, U46
  5. eMMC RAM, U1
  6. Dual QSPI Flash, U32, U33
  7. Crypto Authentication IC, U19
  8. OPTIGA Trust M Authentication IC, U16
  9. EEPROM MAC Address, U14
  10. USB2.0 Transceiver, U2
  11. Gigabit Ethernet Transceiver, U17
  12. B2B Connector, J2
  13. B2B Connector, J3
  14. B2B Connector, J1
  15. B2B Connector, J4
  16. Power Terminal, J5
  17. Configurable Regulator, U20

Initial Delivery State

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Note

Only components like EEPROM, QSPI flash can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty



Scroll Title
anchorTable_OV_IDS
titleInitial delivery state of programmable devices on the module

Scroll Table Layout
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cellHighlightingtrue

Storage device name

Content

Notes

Quad SPI Flash

Not Programmed


EEPROMProgrammed

MAC Address

System Controller CPLDProgrammedIntel MAX 10
PL DDR4 SDRAMNot Programmed
PS DDR4 SDRAMNot Programmed
eMMCNot Programmed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.


Scroll Title
anchorTable_OV_CNTRL
titleController signal.

Scroll Table Layout
orientationportrait
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Function

SchematicConnected toDirectionDescription

Boot Mode

MODE0...3B2B, J3AInput
ResetPERST0B2B, J1BInput
PGOOD

Power GoodPG_
VCCINT
SOM
CPLD
B2B,
U46
J2BOutput
Power EnableEN_
VCCINT
SOM
CPLD
B2B,
U46
J2BInput

Signals, Interfaces and Pins

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For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note

Modules has mostly B2B Connector with Interface subsections

Hybride Modules have B2B Connector with Interface subsections and additional "real" connector

Carrier has  B2B connector (maybe not all interfaces like modules has) and "real" connectors

Evaluation boards has only "real" connectors

Modules with main SoC have an additional MIO section, where dedication MIO Pin assignment will be shown


Manual ResetMR

B2B, J2B

CPLD, U46

Output

Output


Power SignalPG_+3.3VB2B, J2BOutput
Battery SupplyV_BATBank PSCONFIGInput
Control SignalDONEB2B, J3BOutputPull up
Control SignalPOR_BB2B, J3BInputPull up
Initialization SignalINIT_BB2B, J3BOutputPull up
Program SignalPROG_BB2B, J3BOutputPull up
Reset SignalSRST_BB2B, J3BInputPull up


Signals, Interfaces and Pins

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idComments

For subsection examples see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-Signals,InterfacesandPins

Note

Modules has mostly B2B Connector with Interface subsections

Hybride Modules have B2B Connector with Interface subsections and additional "real" connector

Carrier has  B2B connector (maybe not all interfaces like modules has) and "real" connectors

Evaluation boards has only "real" connectors

Modules with main SoC have an additional MIO section, where dedication MIO Pin assignment will be shown


Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Board to Board (B2B) I/Os

FPGA bank number and number of I/O signals connected to the B2B connector:

Scroll Title
anchorTable_SIP_B2B
titleGeneral PL I/O to B2B connectors information
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueFPGA BankB2B ConnectorI/O Signal CountVoltage LevelNotesJTAG Interface

JTAG access to the UltraScale+ MPsoC FPGA through B2B connector J3B.

Scroll Title
anchorTable_SIP_JTGB2B
titleJTAG pins connectionGeneral PL I/O to B2B connectors information

Scroll Table Layout
orientationportrait
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sortEnabledfalse
cellHighlightingtrue

Bank
JTAG Signal
Type

B2B Connector

TMSJ3B- D59
TDIJ3B- D57
TDOJ3B- D58
TCK

J3B- D56

JTAG access to the system controller CPLD, Intel MAX10 FPGA(U46) through B2B connector J2B.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrue

JTAG Signal

B2B Connector

TCK_MAX10J2B- D56TMS_MAX10J2B- D57TDO_MAX10J2B- D58TDI_MAX10

J2B- D59

JTAGENPulled Up

MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

I/O Signal Count

VoltageNotes

64

HP

JM2

48x Single Ended, 24x  LVDS Pairs

Variable

Max voltage 1.8V
65

HP

JM2

24x Single Ended, 12x  LVDS Pairs

Variable

Max voltage 1.8V

65

HP

JM3

24x Single Ended, 12x  LVDS Pairs

Variable

Max voltage 1.8V

66

HP

JM1

48x Single Ended, 24x  LVDS Pairs

Variable

Max voltage 1.8V
500MIOJM126x Single Ended1.8VMIO0...25

501

MIO

JM1

6x Single Ended

Variable

Max voltage 3.3V

505

GTR

JM3

16x Single Ended, 8x  LVDS Pairs

0.85V

4x Lanes

505

GTR CLK

JM3

2x differential Clock

-



For detailed information about the pin-out, please refer to the Pin-out table.

MGT Lanes

The Xilinx Zynq UltraScale+ device used on the TE0865 module has 4x Lanes MGT transceivers connected to Bank 505 PSGTR. All 4x lanes are wired directly to B2B connector J3B consisting of one transmit and one receive (TX/RX) differential pairs, four signals total per one MGT lane. Furthuremore, MGT clocks are sourced by oscillators U3 and U4 at 27 and 100 MHz respectively.
Following table lists lane number, FPGA bank number, transceiver type, signal schematic name, board-to-board pin connection and FPGA pins connection:

MIO PinConnected toB2BNotesMIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI

Scroll Title
anchorTable_SIP_MIOsMGT
titleMIOs pinsMGT Lanes connection

Scroll Table Layout
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cellHighlightingtrue

MIO
Bank
Pin
Connected toNotesMIO0...5QSPI Flash, U32MIO6...11QSPI, Flash, 33MIO13...22eMMC, U1
MIO23B2B, J2AU_INIT
MIO24...25B2B, J3BI2C U via Voltage Transform, U15
MIO26...27B2B, J2AUART0_RX
MIO28...29B2B, J2AUART1_RX
MIO30...31B2B, J2AI2C M via Voltage Transform, U12
MIO32...37B2B, J2AGPIO0...5
MIO38B2B, J2AM_INIT
MIO39...42B2B, J2BSD
MIO43B2B, J2APS_RSTn
MIO44...51B2B, J2ASD
MIO52...63USB2.0, U2USB2.0
MIO64...77ETH PHY, U17ETH PHY

Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes10PWR_PL_OKJ2-120 Scroll Title
anchorTable_SIP_TPs
titleTest Points Information
Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueTest PointSignalNotes
Signal NameB2B PinNote
505
(PSGTR)



MGT Lane  0 
  • GTR_RX0_P
  • GTR_RX0_N
  • GTR_TX0_P
  • GTR_TX0_N
  • J3B-D39
  • J3B-D40
  • J3B-C38
  • J3B-C39

MGT Lane 1
  • GTR_RX1_P
  • GTR_RX1_N
  • GTR_TX1_P
  • GTR_TX1_N
  • J3B-D36
  • J3B-D37
  • J3B-C35
  • J3B-C36

MGT Lane 2
  • GTR_RX2_P
  • GTR_RX2_N
  • GTR_TX2_P
  • GTR_TX2_N
  • J3B-D33
  • J3B-D34
  • J3B-C32
  • J3B-C33

MGT Lane 3
  • GTR_RX3_P
  • GTR_RX3_N
  • GTR_TX3_P
  • GTR_TX3_N
  • J3B-D30
  • J3B-D31
  • J3B-C29
  • J3B-C30

MGT_CLK0MGT505_CLK0 (P/N)Oscillator, U327 MHz
MGT_CLK1MGT505_CLK1 (P/N)Oscillator, U4100 MHz
MGT_CLK2
  • MGT505_CLK2_P
  • MGT505_CLK2_N
  • J3A-A29
  • J3A-A30

MGT_CLK3
  • MGT505_CLK2_P
  • MGT505_CLK2_N
  • J3A-B30
  • J3A-B31


There are 3 clock sources for the GTR transceivers. B505_CLK0 is connected directly to B2B connector JM3, so the clock can be provided by the carrier board. Clocks B505_CLK1 and B505_CLK3 are provided by the on-board clock generator (U10). As there are no capacitive coupling of the data and clock lines that are connected to the connectors, these may be required on the user’s PCB depending on the application.JTAG Interface

JTAG access to the UltraScale+ MPsoC FPGA through B2B connector J3B.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

Scroll Table Layout
orientationportrait
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cellHighlightingtrue

JTAG Signal

B2B Connector

TMSJ3B- D59
TDIJ3B- D57
TDOJ3B- D58
TCK

J3B- D56


JTAG access to the system controller CPLD, Intel MAX10 FPGA(U46) through B2B connector J2B.

Scroll Title
anchorTable_SIP_JTG
titleJTAG pins connection

Scroll Table Layout
orientationportrait
sortDirectionASC
repeatTableHeadersdefault
style
widths
sortByColumn1
sortEnabledfalse
cellHighlightingtrue

JTAG Signal

B2B Connector

TCK_MAX10J2B- D56
TMS_MAX10J2B- D57
TDO_MAX10J2B- D58
TDI_MAX10

J2B- D59

JTAGENPulled Up


I2C Addresses

Scroll Title
anchorTable_SIP_I2CADD
titleI2C addresses
TP1...2+12.0VTP3...4+3.3VTP5...6+3.3V_SWTP7...8+2.3VTP9...10+1.8VTP11...12+1.8V_AUXTP13...14+1.8V_VCCADCTP15...16+0.85V_VCCINTTP17...18+1.2V_PL_DDRTP19...20+2.5V_PL_DDRTP21...22+0.85V_GTR_AVCC_PSTP23...24+1.8V_GTR_AVTT_PSTP25...26+1.8V_AUX_PSTP27...28+1.2V_PLL_PSTP29...30+1.2V_PS_DDRTP31...32+2.5V_PS_DDRTP33...34VREFA_DDR_PSTP35...36VREFA_DDR_PLTP37...38VTT_DDR_PSTP39...40VTT_DDR_PLTP41...42+0.9V_GTH_AVCCTP43...44+1.8V_GTH_AUXTP45...46+1.2V_GTH_AVTTTP47...48+0.9V_GTY_AVCCTP49...50+1.8V_GTY_AUXTP51...52+1.2V_GTY_AVTT

On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example: #ClockSources, #CPLD, #QuadSPIFlash

Scroll Title
anchorTable_OBP
titleOn board peripherals

Scroll Table Layout
orientationportrait
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Chip/Interface
I2C AddressDesignatorNotes
Intel MAX 10
0x53
U46
U14
PL DDR4 SDRAM

U9, U10, U28, U29

PS DDR4 RAMU5...U8, U11Dual QSPI FlashU32, U33eMMC RAMU1USB2.0 TransceiverU2Gigabit Ethernet TransceiverU17EEPROMU14Crypto AuthenticationU19OPTIGA AuthenticationU16MEMS Oscillator,
EEPROM
0x30U16OPTIGA Trust M
0x4EU20Configurable Regulator


MIO Pins

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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

CPLD

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Note

Link always to CPLD Documentation, because CPLD Firmware can be changed during the time. Describe used device type and basic Pin connection to B2B and Main FPGA

you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

MIO PinConnected toB2BNotes
MIO12...14

SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

J2QSPI



Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

Scroll Title
anchorTable_OBPSIP_SPIMIOs
titleQuad SPI interface MIOs and pins

Scroll Table Layout
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MIO Pin
SchematicU?? PinNotes

Crypto Authentication

OPTIGA Authentication

EEPROM
Connected toNotes
MIO0...5QSPI Flash, U32
MIO6...11QSPI, Flash, U33
MIO13...22eMMC, U1
MIO23B2B, J2AU_INIT
MIO24...25B2B, J3BI2C  via Voltage Transform, U15
MIO26...27B2B, J2AUART0_RX
MIO28...29B2B, J2AUART1_RX
MIO30...31B2B, J2AI2C via Voltage Transform, U12
MIO32...37B2B, J2AGPIO0...5
MIO38B2B, J2AM_INIT
MIO39...42B2B, J2BSD
MIO43B2B, J2APS_RSTn
MIO44...51B2B, J2ASD
MIO52...63USB2.0, U2USB2.0
MIO64...77ETH PHY, U17ETH PHY


Test Points

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you must fill the table below with group of Test Point which are indicated as TP in a schematic. If there is no Test Point remarked in the schematic, delet the Test Point section.

Example:

Test PointSignalB2BNotes
10PWR_PL_OKJ2-120



Scroll Title
anchorTable_SIP_TPs
titleTest Points Information

Scroll Table Layout
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sortEnabledfalse
cellHighlightingtrue

Test PointSignalNotes
TP1...2+12.0V
TP3...4+3.3V
TP5...6+3.3V_SW
TP7...8+2.3V
TP9...10+1.8V
TP11...12+1.8V_AUX
TP13...14+1.8V_VCCADC
TP15...16+0.85V_VCCINT
TP17...18+1.2V_PL_DDR
TP19...20+2.5V_PL_DDR
TP21...22+0.85V_GTR_AVCC_PS
TP23...24+1.8V_GTR_AVTT_PS
TP25...26+1.8V_AUX_PS
TP27...28+1.2V_PLL_PS
TP29...30+1.2V_PS_DDR
TP31...32+2.5V_PS_DDR
TP33...34VREFA_DDR_PS
TP35...36VREFA_DDR_PL
TP37...38VTT_DDR_PS
TP39...40VTT_DDR_PL
TP41...42+0.9V_GTH_AVCC
TP43...44+1.8V_GTH_AUX
TP45...46+1.2V_GTH_AVTT
TP47...48+0.9V_GTY_AVCC
TP49...50+1.8V_GTY_AUX
TP51...52+1.2V_GTY_AVTT


On-board Peripherals

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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection by assigning advance link using: #NameOfTheSection

Example: #ClockSources, #CPLD, #QuadSPIFlash


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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
Intel MAX 10 CPLDU46
PL DDR4 SDRAM

U9, U10, U28, U29


PS DDR4 SDRAMU5...U8, U11
Dual QSPI FlashU32, U33
eMMC MemoryU1
USB2.0 TransceiverU2
Gigabit Ethernet TransceiverU17
EEPROMU14
Crypto AuthenticationU19
OPTIGA AuthenticationU16
MEMS OscillatorU3, U4, U13, U18, U31, U34



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For example subsections see: <Series Name> TRM Template section examples#%3CSeriesName%3ETRMTemplatesectionexamples-On-boardPeripherals

System Controller CPLD

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Note

Link always to CPLD Documentation, because CPLD Firmware can be changed during the time. Describe used device type and basic Pin connection to B2B and Main FPGA


The TE0865 is equipped with an Intel MAX 10 as System Controller CPLD (U46). Please check further information in the TE0865 CPLD page.

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titleCPLD pin connections

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BankSchematicConnectced toNotes
Bank 1AVCCIO1A3.3V
Bank 1BTCK_MAX10B2B, J2B
TMS_MAX10B2B, J2B
TDO_MAX10B2B, J2B
TDI_MAX10B2B, J2B
VCCIO1B3.3V
Bank 2EN_VTT_DDR_PLRegulator, U26
EN_+2.5V_PL_DDRRegulator, U22Enable Power DDR4 PL
EN_+1.2V_PL_DDRRegulator, U24Enable Power DDR4 PL
PG_+1.2V_PL_DDRRegulator, U24Power Good DDR4 PL
EN_+1.8V_AUX_PSRegulator, U43
EN_SOMB2B, J2BMain 'Power Enable' signal
PG_SOMB2B, J2BMain 'Power Good' signal
SC_EXT_2...3B2B, J2B
PG_VCCINTRegulator, U20Configurable Regulator
LTM_FAULTRegulator, U20Configurable Regulator
MR

B2B, J2B

Regulator, U51


Bank 3SMB_ALERTnRegulator, U20Configurable Regulator
PG_+2.5V_PL_DDRRegulator, U22Power Good DDR4 PL
LTM_RUNP_ENRegulator, U20Configurable Regulator
M_SDAI2C  BusB2B, J2A via level shifter (U12)
M_SCLI2C  BusB2B, J2A via level shifter (U12)
RST_SYSnDiod, U53BReset
EN_+0.9V_GTH_AVCCRegulator, U35
EN_+0.9V_GTY_AVCCRegulator, U38
PG_+1.2V_PS_DDRRegulator, U25Power Good DDR4 PS
PG_+0.9V_GTH_AVCCRegulator, U35
PG_+0.9V_GTY_AVCCRegulator, U38
EN_+3.3V_SWRegulator, U52Secondary Power
EN_+1.2V_PLL_PSRegulator, U42
PG_+1.8V_GTR_AVTT_PSRegulator, U47
PG_+1.8VRegulator, U41
EN_+2.5V_PS_DDRRegulator, U23Enable Power DDR4 PS
PG_+1.2V_GTY_AVTTRegulator, U39
EN_+1.2V_GTY_AVTTRegulator, U39
M_INTB2B, J2A
EN_+1.8V_VCCADCRegulator, U49
PG_+0.85V_GTR_AVCC_PSRegulator, U48
EN_VTT_DDR_PSRegulator, U27
EN_+1.8VRegulator, U41
EN_+1.8V_GTY_AUXRegulator, U40
PG_+2.3VRegulator, U45
Bank 6VCCIO63.3V
Bank 5EN_+1.8V_GTR_AVTT_PSRegulator, U47
EN_+1.8V_GTH_AUXRegulator, U37
EN_+1.8V_AUXRegulator, U50
EN_+1.2V_GTH_AVTTRegulator, 36
PG_+1.2V_GTH_AVTTregulator, U36
+3.3V_SWeMMC, U1
EN_+1.2V_PS_DDRRegulator, U25Power Good DDR4 PS
EN_+0.85V_GTR_AVCC_PSRegulator, U48
PG_+1.2V_GTH_AVTTRegulator, U48
EN_VCCINTRegulator, U20
EN_+2.3VRegulator, U45
PG_+1.8V_AUXRegulator, U50
PG_+2.5V_PS_DDRRegulator, U23Power Good DDR4 PS


Dual QSPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

The TE0865 is equipped with dual 128 Mb (256 Mb) QSPI flash memory, U32 and U33 for configuration and operation storage.

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titleQuad SPI interface MIOs and pins

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DesignatorPinSchematicNotes
U32CLKMIO0
DI/IO0 MIO4
DO/IO1MIO1
nWP/IO2MIO2
nHOLD/IO3MIO3
nCSMIO5
U33CLKMIO12
DI/IO0 MIO8
DO/IO1MIO9
nWP/IO2MIO10
nHOLD/IO3MIO11
nCSMIO7


eMMC Memory

The TE0865 is equipped with an eMMC Flash memory IC(U1) connected to the PS MIO pins MIO13..MIO22. 

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titleeMMC connections

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DesignatorPinSchematicConnected to Notes
U32CLKMMC-CCLKMIO22
nRESETRST_PERn-PS_RSTn, PS_SYSn
CMDMMC-CMDMIO21
DAT0...7MMCD0...7MIO13...20


Gigabit Ethernet

On-board Gigabit Ethernet PHY (U17) is provided with Marvell Alaska 88E1512 IC (U17). The Ethernet PHY RGMII interface is connected to the ZynqMP Ethernet3 PS GEM3. I/O voltage is fixed at 1.8V for HSTL signaling. The reference clock input of the ETH is supplied from an on-board 25.00 MHz oscillator (U18).

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titleGigaBit Ethernet connection

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PinSchematicConnected toNote
MDIP0...3

PHY_MDI0...3

B2B, J3A


MDC

ETH_MDC

MIO76


MDIOETH_MDIOMIO77
S_INS_INN.C
S_OUTS_OUTN.C
TXD0..3ETH_TXD0...3MIO65...68
TX_CTRLETH_TXCTLMIO69
TX_CLKETH_TXCKMIO64
RXD0...3ETH_RXD0...3MIO71...74
RX_CTRLETH_RXCTLMIO75
RX_CLKETH_RXCKMIO70
LED1PHY_LED1B2B, J3A
RESETnETH_RSTMIO24
XTAL_INETH_CLKOscillator, U18Input Clock of ETH Transciever
nRESETRST_PERnB2B, J2APS_RSTn, PS_SYSn


USB2.0 Transceiver

Hi-speed USB2.0 transceiver (U2) is provided with USB3340 from Microchip. The transceiver is connected to the PS MIO via MIO52..63. The I/O voltage is fixed at 3.3V (VBAT) and PHY reference clock input is supplied from the on-board 24.00 MHz oscillator (U13).

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title General overview of the USB PHY signals

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 PinSchematicMIOB2B NameNotes
RESETBRST_PERn-
RST_PERn
VBATVBAT-
3.3V
CPENUSB_CPEN-B2B, J3A
VBUSUSB_VBUS-B2B, J3A
IDUSB_ID-B2B, J3A
DP, DM

USB_DP

USB_ DM

-B2B, J3A
REFCLKUSB_CLK24_PHY--24.00MHz from on-board oscillator (U13).
REFSEL[0..2]---Reference clock frequency select, all set to 1.8V selects 24 MHz.
DATA0...7USB_DATA0...7

MIO 56,57,54, 59...62

-USB Data
STPUSB_STPMIO58-
NXTUSB_NXTMIO55-
DIUSB_DIMIO53-
CLKOUTUSB_CLKOUTMIO52-


EEPROM

There is an EEPROM (U14) provided on the module TE0865 for storing MAC Address. The EEPROM has the I2C bus address 0x53.

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titleI2C EEPROM interface MIOs and pins

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MIO PinSchematicU25 PinNotes
MIO39I2C_SDASDA
MIO38I2C_SCLSCL


Crypto Authentication

The TE0865 is equipped with an authentication IC, ATECC608A (U19) which includes an EEPROM array for storage of up to 16 keys, certificates, miscellaneous read/write, read-only or secret data, consumption logging, and security configurations. Access to the various sections of memory can be restricted in a variety of ways and then the configuration can be locked to prevent changes.

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titleCrypto Authentication connection

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PinSchematicConnected toNotes
SDAM_SDAB2B, J2AM_SDA_PS
SCLM_SDAB2B, J2AM_SCL_PS


OPTIGA Authentication

The TE0865 is equipped with an OPTIGA Trust M  IC, SLS32AIA010MH (U16). The OPTIGA Trust M comes with up to 10kB of user memory that can be used to store X.509 certificates and data. OPTIGA Trust M is based on Common Criteria (CC) Certified EAL6+ (high) hardware enabling it to prevent physical attacks on the device itself and providing high assurance that the keys or arbitrary data stored cannot be accessed by an unauthorized entity. The OPTIGA Trust M is connected via I2C with address of 0x30.

Notes
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titleI2C EEPROM interface MIOs and pinsOPTIGA Authentication connection

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MIO
PinSchematic
U?? Pin
Connected toNotes
Scroll Title
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titleI2C address for EEPROM
SDAM_SDAB2B, J2A
SCLM_SDAB2B, J2A
RSTRST_SECnB2B, J2APS_RSTn
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MIO PinI2C AddressDesignator


PL DDR4 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? TE0865 SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and four volatile DDR4 SDRAM ICs connected to Programmable Logic(PL) for operations, storing and streaming data.

  • Part number:  MT40A1G16RC-062E*
  • Supply voltage: 1.2V
  • Speed:  
  • NOR Flash
    • Temperature: 
  • 3200 MT/s*
  • Temperature: -40 ~ 95 °C*

* depends on assembly version

PS DDR4 SDRAM

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Notes :

Minimum and Maximum density of DDR3 SDRAM must be mentioned for other assembly options. (pay attention to supported address length for DDR3)

The TE???? TE0865 SoM has ??? GByte volatile DDR3 SDRAM IC for storing user application code and five volatile DDR4 SDRAM ICs connected to Processing System (PS) for operations, storing and streaming data.

  • Part number:   MT40A1G16RC-062E*
  • Supply voltage: 1.2V
  • Speed:  NOR Flash3200 MT/s*
  • Temperature:

Ethernet

Scroll Title
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titleEthernet PHY to Zynq SoC connections
  • -40 ~ 95 °C*

* depends on assembly version

Clock Sources

Scroll Table LayoutorientationportraitsortDirectionASCrepeatTableHeadersdefaultstylewidthssortByColumn1sortEnabledfalsecellHighlightingtrueU?? Pin Signal NameConnected toSignal DescriptionNoteeMMC

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titleeMMC InformationOsillators

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Designator
SchematicU?? PinNotes
Clock Sources
KHz
DescriptionFrequencyNote
U3MEMS Oscillator27 MHzMGT_CLK0
U4MEMS Oscillator100 MHzMGT_CLK1
U13MEMS Oscillator24 MHzUSB_CLK
U18MEMS Oscillator25 MHzETH_CLK
U31MEMS Oscillator200 MHzDDR4 Clock
U34MEMS Oscillator33.33 MHzPS REF CLK
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titleOsillators
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DesignatorDescriptionFrequencyNote
MHzMHz


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of xx 3.0 A for system startup is recommended.

Power Consumption

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titlePower Consumption

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Power Input PinTypical Current
VINTBD*

* TBD - To Be Determined

Power Distribution Dependencies

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Power Input PinTypical Current
VINTBD*


* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Distribution


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Power-On Sequence

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titlePower DistributionSequency


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Power-On Sequence


Voltage Monitor Circuit

The LTM4700 (U20) is a dual 50A or single 100A step-down µModule(power module) DC/DC regulator featuring remote configurability and telemetry-monitoring of power management parameters over standard I2C-based digital interface protocol.

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titlePower SequencyVoltage Monitor Circuit


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4


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titleVoltage Monitor Circuit
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Power Rails

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titleModule power rails.

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-91
Power Rail Name

B2B J1 Pin

B2B J2 Pin

B2B J3 Pin

B2B J4 PinDirectionNotes
VCCIO_67D10---In
VCCIO_66D20---In
VCCIO_64D35---In

VCCIO_65

D45

D45---In
VCCIO_91-A6,--In
VCCIO_90-B10--In
VCCIO_89-A21--In
V_IO_CFG-A45--In
+1.2V_PL_DDR-B44--Out
VCCIO_68-C29--In
VCCIO_88-A6,D44--In
VCCIO_90+3.3V-B10D60--InOut
+1.8VVCCIO_89-
A21D60-Out


Bank Voltages

InVIO_CFG
scroll-title
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Table_
-A45--In+1.2V_PL_DDR-B44--OutVCCIO_68-C29--InVCCIO_88-D44--In+3.3V-D60--Out+1.8V-D60-Out

Bank Voltages

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titleZynq SoC bank voltages.
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Bank          

Schematic Name

Voltage

Notes64 HPVCCIO_64max 1.8 V65 HP VCCIO_65max 1.8 V66 HPVCCIO_66max 1.8 V67 HP VCCIO_67max 1.8 V68 HPVCCIO_68max 1.8 V69 HP VCCIO_691.2 V70 HPVCCIO_701.2 V71 HPVCCIO_711.2 V88 HDVCCIO_88max 3.3VZU17 Bank 90 HD89 HDVCCIO_88max 3.3 VZU17 Bank 91 HD90 HDVCCIO_88max 3.3VZU17 Bank 93 HD91 HDVCCIO_88max 3.3VZU17 Bank 94 HD
PWR_BV
titleZynq SoC bank voltages.

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Bank          

Schematic Name

Voltage

Notes
64 HPVCCIO_64max 1.8 V
65 HP VCCIO_65max 1.8 V
66 HPVCCIO_66max 1.8 V
67 HP VCCIO_67max 1.8 V
68 HPVCCIO_68max 1.8 V
69 HP VCCIO_691.2 V


70 HPVCCIO_701.2 V


71 HPVCCIO_711.2 V
88 HDVCCIO_88max 3.3VZU17 Bank 90 HD
89 HDVCCIO_88max 3.3 VZU17 Bank 91 HD
90 HDVCCIO_88max 3.3VZU17 Bank 93 HD
91 HDVCCIO_88max 3.3VZU17 Bank 94 HD
128 GTYMGTAVCC_L0.9 V
129 GTYMGTAVCC_L0.9 V
224 GTHMGTAVCC_RS0.9 V
225 GTHMGTAVCC_RS0.9 V
228 GTHMGTAVCC_RN0.9 V
229 GTHMGTAVCC_RN0.9 V
500 PSMIOVCCO_PSIO0_5001.8 V
501 PSMIOVCCO_PSIO0_501max 3.3 V
502 PSMIOVCCO_PSIO0_5021.8 V
504 PSDDRVCCO_PSDDR_5041.2 V
505 PSGTRPS_MGTRAVCC0.85 V



Board to Board Connectors

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  • This section is optional and only for modules.

  • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors

    Include Page
    6 x 6 SoM LSHM B2B Connectors
    6 x 6 SoM LSHM B2B Connectors

Include Page
7.5 x 10 ADM6/ADF6 B2B Connectors
7.5 x 10 ADM6/ADF6 B2B Connectors

Technical Specifications

Absolute Maximum Ratings

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titlePS absolute maximum ratings

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SymbolsDescriptionMinMaxUnitNote
VCCRInput Supply Voltage5.7516VB2B, J5
V_IO_CFGConfig Voltage-0.53.4VB2B,J3
VCCIO_64Bank 64 Supply Voltage-0.52VB2B,J1
VCCIO_65Bank 65 Supply Voltage-0.52VB2B,J1
VCCIO_66Bank 66 Supply Voltage-0.52VB2B,J1
VCCIO_67Bank 67 Supply Voltage-0.52VB2B,J1
VCCIO_68Bank 68 Supply Voltage-0.52VB2B,J2
T_STGStorage Temperature-4085
128 GTYMGTAVCC_L0.9 V129 GTYMGTAVCC_L0.9 V224 GTHMGTAVCC_RS0.9 V225 GTHMGTAVCC_RS0.9 V228 GTHMGTAVCC_RN0.9 V229 GTHMGTAVCC_RN0.9 V500 PSMIOVCCO_PSIO0_5001.8 V501 PSMIOVCCO_PSIO0_501max 3.3 V502 PSMIOVCCO_PSIO0_5021.8 V504 PSDDRVCCO_PSDDR_5041.2 V505 PSGTRPS_MGTRAVCC0.85 VBoard to Board Connectors Page properties
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  • This section is optional and only for modules.

    • use "include page" macro and link to the general B2B connector page of the module series,

    For example: 6 x 6 SoM LSHM B2B Connectors
    Include PagePD:6 x 6 SoM LSHM B2B ConnectorsPD:6 x 6 SoM LSHM B2B Connectors

    Technical Specifications

    Absolute Maximum Ratings

    V
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    titlePS absolute maximum ratings
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    SymbolsDescriptionMinMaxUnit
    VVVVVVV
    °C


    Recommended Operating Conditions

    Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

    Scroll Title
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    titleRecommended operating conditions.

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    ParameterMinMaxUnitsReference Document
    VCCR11.512.5VSee ???? datasheets.VSee  ???? datasheet.VSee  ???? datasheet.VSee  ???? datasheet.VSee  ???? datasheet.VSee  ???? datasheet.V LTM4700 (U20) datasheet.
    V_IO_CFG1.143.4V
    VCCIO_640.951.9V
    VCCIO_650.951.9V
    VCCIO_660.951.9V
    VCCIO_670.951.9V
    VCCIO_680.951.9V
    T_OPT085°CSee components datasheetSee  ???? datasheet.°CSee  ???? datasheet.°CSee  ???? datasheet.



    Components are mainly classified in 3 temperature groups, according to range specifications: commercial: 0°C - 75°C extended: 0°C - 85°C industrial: -40°C - 85°C

    Classification of the module can be locked up here: Article Number Information i.e.: TE0803-03-5D"I"21-AS (The I indicates industrial)

    The actual operation temperature range depends on the FPGA/SoC design/utilization and cooling, as well as other variables. Please note: These are only indications!

    Physical Dimensions

    • Module size: 75 mm × 100 mm.  Please download the assembly diagram for exact numbers.

    • Mating height with standard connectors: 5 mm.

    PCB thickness: 2 mm.

    Page properties
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    In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

    For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

    https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

    Note

    For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .



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    titlePhysical Dimension


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    Currently Offered Variants 

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    Set correct link to the shop page overview table of the product on English and German.

    Example for TE0706:

        ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

        DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706


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    titleTrenz Electronic Shop Overview

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    Trenz shop TE0865 overview page
    English pageGerman page


    Revision History

    Hardware Revision History

    Page properties
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    Set correct links to download  Carrier, e.g. TE0706 REV02:

      TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

    Note:

    • Date format:  YYYY-MM-DD

    • Example: 

      DateRevisionChangesDocumentation Link
      2020-11-25REV02
      • Resistors R14 and R15 was replaced by 953R (was 5K1)
      • Resistor R5 was replaced by 5K1, R8 by 953R (was 9K09 and 1K69 respectively)
      		REV02



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    titleBoard hardware revision number.


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    titleHardware Revision History

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    DateRevisionChangesDocumentation Link
    2021-04-15REV01
    Initial ReleaseREV01
    2021-10-21REV02
    • Improved PCB trace to simplify production with increased reliability
    • All pull down resistors on DCDC enable inputs changed to 1K
    		REV02
    Initial Release


    Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

    Document Change History

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    Document change history.

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    • Key features: default DDR4 capacity changed to 4GB

    • Added a notes in PL DDR4 SDRAM and PL DDR4 SDRAM chapter

    • Minor change in Overview chapter
    2024-02-07

    V.71

    John Hartfiel 

    • Correction Maximum DDR Speed on Key features according AMD Datasheet (still depends assembled ZynqMP)


    2023-10-24


    v.69

    John Hartfiel 

    • Correction Overview Picture GTH B2B connection

    2023-07-05


    v.68

    Vadim Yunitski

    • Updated table "CPLD Pin Connections": added signals EN_SOM and PG_SOM; SC_EXT_1 and SC_EXT_4 removed.
    • Updated table "Controller signals": PG_VCCINT and EN_VCCINT replaced by PG_SOM and EN_SOM. Description updated respectivelly
    • Block diagram updated: added PG_SOM and EN_SOM; SC_EXT_1 and SC_EXT_4 removed.
    2022-10-17


    		v.67


    		JH


    • Update link to the download area

    2022-05-30v.66ED
    • Update to the latest version
    anchorTable_RH_DCH
    titleDocument change history.
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    DateRevisionContributorDescription

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    infoTypeCurrent version
    prefixv.
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    showVersionsfalse

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    showVersionsfalse

    • change list

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