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Note for Download Link of the Scroll ignore macro:


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Download PDF version of this document.


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Table of Contents

Table of Contents

Overview

The Trenz Electronic TEF0003 is A a FPGA Mezzanine Card (FMC) integrated with a an Artix 7 FPGA, 512 Mb Flash Memory. 

Refer to http://trenz.org/tef0003-info for the current online version of this manual and other available documentation.

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Notes :

Key Features

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Note:
 'description: Important components and connector or other Features of the module
→ please sort and indicate assembly options

Key Features'  must be split into 6 main groups:

  • FPGA/Module
    • Package:
    • Speed:
    • Temperature:
  • RAM/Storage
    • E.g. SDRAM, SPI
  • On Board
    • E.g. CPLD, PLL
  • Interface
    • E.g. ETH, USB, B2B, Display port
  • Power
    • E.g. Input supply voltage
  • Dimension
  • FPGA: Xilinx Artix 7 (XC7A100T)
    • Package:  FGG484 (Compatible with 
    • Speed: -1 (Slowest)
    • Temperature: Industrial Grade (–40°C to +100°C) 
  • RAM/Storage:
    • 1x NOR SPI FLASH (128M x 4)
    • 1x EEPROM (16K x 8)
  • On Board:
    • 4x Deserializer IC (3.12 Gbps)
    • 4x I2C and SMBus I/O Expander
    • 1x Programable Clock Generator
    • 1x Clock Generator
  • Interface:
    • 2x VITA 57 SEAM/SEAF Series systemSeries 
    • 4x Coaxial connectorsConnectors
  • Power:
    • 4x Voltage Regulators 
    • 3.3 Supply Voltage
  • Dimension:
    • 72 mm x 65 mm

Block Diagram

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add drawIO object here.

Note

For more information regarding how to draw a diagram, Please refer to "Diagram Drawing Guidline" .


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titleTEF0003 block diagram


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Main Components

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Notes :

  • Picture of the PCB (top and bottom side) with labels of important components
  • Add List below


Note

For more information regarding how to add board photoes, Please refer to "Diagram Drawing Guidline" .


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Scroll Title
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titleTEF0003 main components


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  1. Coaxial Connectors, J2-5
  2. SPI Flash, U9
  3. Xilinx Artix 7 FPGA, U1
  4. Lattice MachXO FPGA, U15
  5. Vita 57 ConnectorFMC Adapter, J1
  6. EEPROM, U4
  7. I2C Switches, U2, U17-20
  8. Jumper, J7
  9. Serializer, U5-8
  10. Connector Header, J8
  11. Oscillator 25MHz, U11
  12. Programmable Clock Generator, U10
  13. Vita 57 ConnectorFMC Adapter, J6

Initial Delivery State

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Notes :

Only components like EEPROM, QSPI flash and DDR3 can be initialized by default at manufacture.

If there is no components which might have initial data ( possible on carrier) you must keep the table empty

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Storage device name

Content

Notes

SPI Flash

Not programmed 


EEPROMNot Programmed 


Clock GeneratorProgrammed


Configuration Signals

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  • Overview of Boot Mode, Reset, Enables.

...

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titleReset processProcess.

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Signal

B2BI/ONote

MUX_RESET

-
DescriptionNote

PRSNT_TOP

Lattice MachXO Configuration Pin


PROG_BArtix 7 Configuration PinPulled up to 1.8


Signals, Interfaces and Pins

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Notes :

  • For carrier or stand-alone boards use subsection for every connector type (add designator on description, not on the subsection title), for example:
    • SD
    • USB
    • ETH
    • FMC
    • ...
  • For modules which needs carrier use only classes and refer to B2B connector if more than one is used, for example
    • JTAG
    • UART
    • I2C
    • MGT
    • ...

...

FMC Connectors

FPGA bank number and number of I/O signals connected to the B2B connector:FMC Connectors J1 and J6 which are located on top and bottom of the board.

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titleGeneral PL I/O to B2B connectors FMC Connectors information

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FPGAFPGA BankConnector DesignatorI/O Signal CountVoltage LevelNotes
Artix 7, U116J1B68 Single Ended, 34 Differential1.8V
35J6B68 Single Ended,
34
34 Differential1.8V
Lattice MachXO, U0J1F4 Single Ended 3.3VCPLD
0J6F4 Single Ended 3.3V

...

CPLD


Coaxial Connectors

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titleJTAG pins connectionCoaxial Connectors information

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Designator

JTAG Signal

B2B Connector

FMC_TMSJ6F-TCK
FMC_TDI_TOPJ6F-J1-TDI
FMC_TDO_TOPJ6F-TDO
FMC_TCK

J6F-TCK

JTAGENJ7

MIO Pins

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you must fill the table below with group of MIOs which are connected to a specific components or peripherals, you do not have to specify pins in B2B, Just mention which B2B is connected to MIOs. The rest is clear in the Schematic.

Example:

SchematicConnected toNotes
J2GA_OUTSerializer, U5
J3GB_OUTSerializer, U6
J4GC_OUTSerializer, U7
J5GD_OUTSerializer, U8



JTAG Interface

The Lattice MachXO (U15) is available to meet the requirement of a CPLD, JTAG access to the MachXO is available through FMC Adapter J6. JTAG access to the Artix 7(U1) is available via MachXO, Bank 2.

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titleCPLD JTAG pins connection

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JTAG Signal

B2B Connector

Notes
FMC_TMSJ6F-TCK
FMC_TDI_TOPJ6F-J1-TDI
FMC_TDO_TOPJ6F-TDO
FMC_TCK

J6F-TCK


JTAGENPulled down



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SPI_CS , SPI_DQ0... SPI_DQ3

SPI_SCK

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On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs
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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection

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titleOn board peripherals

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Chip/InterfaceDesignatorNotes
QSPI FlashU11EEPROMU4OscillatorU11,U10

Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

TEF0003 is equipped with a 512Mb Serial NOR Flash (x1/x2/x4) which is provided to store an application on the SPI Flash memory in order to boot the module. The SPI Flash data is connected to Artix 7 FPGBA Bank 14.

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titleQuad SPI interface MIOs and pins

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JTAG Signal

Connected to

Note
TMS

Lattice MachXO, U15

BankArtix 7 FPGA, U1

Bank 2

Bank 0

TDI

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

TDO

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

TCK

Lattice MachXO, U15

Artix 7 FPGA, U1

Bank 2

Bank 0

INIT

Artix 7 FPGA, U1

Pulled up to 1.8


On-board Peripherals

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Notes :

  • add subsection for every component which is important for design, for example:
    • Two 100 Mbit Ethernet Transciever PHY
    • USB PHY
    • Programmable Clock Generator
    • Oscillators
    • eMMCs
    • RTC
    • FTDI
    • ...
    • DIP-Switches
    • Buttons
    • LEDs


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Notes :

In the on-board peripheral table "chip/Interface" must be linked to the corresponding chapter or subsection


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EEPROM

A Microchip 24LC128-I/LC serial EEPROM (U4) is provided for IPMI data. It is accessible via the LPC FMC connector J1 (SCL, SDA).

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titleI2C EEPROM interface MIOs and pins

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Vita 57 ConnectorSchematicU4 PinNotes
J1F-SCLFMC_SCLSCLJ1F-SDAFMC_SDASDAJ1F-GA0GA0A0J1F-GA1GA1A1
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titleI2C address for EEPROM
Chip/InterfaceDesignatorNotes
SPI FlashU9
EEPROMU4
OscillatorsU11
Programmable Clock GeneratorU10


Quad SPI Flash Memory

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Notes :

Minimum and Maximum density of quad SPI flash must be mentioned for other assembly options.

TEF0003 is equipped with a 512Mb Serial NOR Flash (x1/x2/x4) which is provided to store an application in the SPI Flash memory in order to boot the module. The SPI Flash data is connected to Artix 7 via FPGA Bank 14.

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titleQuad SPI interface MIOs and pins

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I2C Address
Schematic
Designator
U9 PinNotes
0x50U4

Clock Sources

SPI-CSCS
SPI-CLKCLK
SPI-DQODI/IO0
SPI_DQ3HOLD/IO3
SPI-DQ2WP/IO2
SPI-DQ1DO/IO1
1.8VVCC


EEPROM

A microchip serial EEPROM (U4) is provided for IPMI data. It is accessible via the LPC FMC connector J1 (SCL, SDA).

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titleI2C EEPROM interface MIOs and pins

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titleOsillators

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DesignatorDescriptionFrequencyNote
U4Oscillator, 25 MHzMHzU10Programmable Clock GeneratorMHz

Programmable Clock Generator

...

U4 PinFMC Pcam AdapterSchematicNotes
SCLJ1F-SCLFMC_SCL
SDAJ1F-SDAFMC_SDA
A0J1F-GA0GA0
A1J1F-GA1GA1
A2--Pulled Low
WP--Pulled Low



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titleProgrammable Clock Generator Inputs and OutputsI2C address for EEPROM

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Si5345A Pin
Signal Name / Description
Connected ToDirectionNote

IN0

Reference input clock.

U11Input25.00 MHz oscillator, SiT8008BI
IN1FMCT_GBTCLK0J6EInputVita 57 Connector
IN2FMCT_GBTCLK1J6EInputVita 57 Connector
IN3FMCT_CLK0J6EInputVita 57 Connector

XAXB

-

GNDInput54.0000 MHz XTAL CX3225SB
SCLKPLL_SCLJ8, U20InputEEPROM Programming
SDAPLL_SDAJ8, U20InputEEPROM Programming
OUT0

GA_PCLK

U5/U1Output

FPGA bank 15

OUT1GB_PCLKU6/U1Output

FPGA bank 15

OUT2GC_PCLKU7/U1Output

FPGA bank 15

OUT3GD_PCLKU8/U1Output

FPGA bank 15

OUT4CLK4_PU1HOutputOUT5GBTCLK0J1E/J6EOutputOUT6

GBTCLK1

J1E/J6E

Output

OUT7GBTCLK0J1EOutputOUT8CLK8Not ConnetedOutput
OUT9CLK9Not ConnetedOutputNot Used

Power and Power-On Sequence

...

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit
Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .

I2C AddressDesignatorNotes
0xA0U4Write operations are enabled 


Clock Sources

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titleOsillators

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DesignatorDescriptionFrequencyNote
U11Oscillator25.00  MHz
U10Programmable Clock GeneratorVariable


Programmable Clock Generator

There is a Silicon Labs I2C programmable clock generator on-board (U10) in order to generate reference clocks for the module. Programming can be done using I2C via PIN header J8.  The I2C Address is 0x69.

Scroll Title
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titleProgrammable Clock Generator Inputs and Outputs

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Si5345A Pin
Signal Name / Description
Connected ToDirectionNote

IN0

Reference input clock.

U11Input25.00 MHz oscillator, SiT8008BI
IN1FMCT_GBTCLK0J6EInputFMC Pcam Adapter
IN2FMCT_GBTCLK1J6EInputFMC Pcam Adapter
IN3FMCT_CLK0J6EInputFMC Pcam Adapter

XAXB

-

GNDInput54.00 MHz CX3225SB
SCLKPLL_SCLJ8, U20InputEEPROM
SDAPLL_SDAJ8, U20InputEEPROM
OUT0

GA_PCLK

U5/U1Output

FPGA bank 15

OUT1GB_PCLKU6/U1Output

FPGA bank 15

OUT2GC_PCLKU7/U1Output

FPGA bank 15

OUT3GD_PCLKU8/U1Output

FPGA bank 15

OUT4CLK4_PU1HOutput
OUT5GBTCLK0J1E/J6EOutput
OUT6

GBTCLK1

J1E/J6E

Output


OUT7GBTCLK0J1EOutput
OUT8/OUT9CLK8/CLK9Pulled lowOutput


Power and Power-On Sequence

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In 'Power and Power-on Sequence' section there are three important digrams which must be drawn:

  • Power on-sequence
  • Power distribution
  • Voltage monitoring circuit


Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

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titlePower Consumption

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Power Input PinTypical Current
3P3VTBD*


* TBD - To Be Determined

Power Distribution Dependencies

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titlePower Distribution

Power Supply

Power supply with minimum current capability of 3 A for system startup is recommended.

Power Consumption

...

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titlePower Consumption

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* TBD - To Be Determined

Power Distribution Dependencies

...

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titlePower Distribution

...

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Power-On Sequence

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titlePower Sequency


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Power

...

-On Sequence

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titleModule power rails.Power Sequency


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Power Rail Name

B2B Connector

JM1 Pin

B2B Connector

JM2 Pin

B2B Connector

JM3 Pin

DirectionNotes

Bank Voltages

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Power Rails

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titleZynq SoC bank voltagesModule power rails.

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Bank          

Schematic Name

Voltage

Notes

...

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Power Rail Name

FMC  Adapter J1G Pin

FMC Adapter J6G Pin

DirectionNotes
12VC35, C37C35, C37Input
3P3VAUXD32D32Input
3P3VD36, D38, D40, C39D36, D38, D40, C39Input

VREFA

H1H1Input
VREFBK1K1Input
VIOBJ39, K40J39, K40Input
VADJH40, G39, F40, E39H40, G39, F40, E39Input


Bank Voltages

Scroll Title
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titleZynq SoC bank voltages.

use "include page" macro and link to the general B2B connector page of the module series,

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Technical Specifications

Absolute Maximum Ratings

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titlePS absolute maximum ratings

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Symbols

Bank          

Description
Schematic Name
Min

Voltage

Max
Notes
UnitVVVVVVVV

Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

Bank 13VCCO_131.8 V
Bank 14VCCO_141.8 V
Bank 15

VCCO_15

1.8 V
Bank 16VCCO_16VADJ1.8 V
Bank 34VCCO_341.8 V
Bank 35VCCO_35VADJ1.8 V
Bank 0VCCO_01.8 V



Technical Specifications

Absolute Maximum Ratings

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titlePS absolute maximum ratings
Scroll Title
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titleRecommended operating conditions.

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Symbols
Parameter
DescriptionMinMax
Units
Unit
Reference DocumentVSee ???? datasheets.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.VSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.°CSee Xilinx ???? datasheet.

Physical Dimensions

  • Module size: 84 mm × 65 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 10 mm.

PCB thickness: 1.54 mm.

3P3VInput Supply Voltage-0.53.75V
T_STGStorage Temperature-4085°C


Recommended Operating Conditions

Operating temperature range depends also on customer design and cooling solution. Please contact us for options.

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titleRecommended operating conditions.

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ParameterMinMaxUnitsReference Document
3P3V2.3753.465V
T_OPR-4085°CSee MT25QU512ABB8E12-0SIT (U9)  datasheet.


Physical Dimensions

  • Module size: 84 mm × 65 mm.  Please download the assembly diagram for exact numbers.

  • Mating height with standard connectors: 10 mm.

PCB thickness: 1.56 mm.

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In 'Physical Dimension'

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In 'Physical Dimension' section, top and bottom view of module must be inserted, information regarding physical dimensions can be obtained through webpage for product in Shop.Trenz, (Download> Documents> Assembly part) for every SoM.

For Example: for Module TE0728, Physical Dimension information can be captured by snipping tools from the link below:

https://www.trenz-electronic.de/fileadmin/docs/Trenz_Electronic/Modules_and_Module_Carriers/5.2x7.6/TE0745/REV02/Documents/AD-TE0745-02-30-1I.PDF

Note

For more information regarding how to draw diagram, Please refer to "Diagram Drawing Guidline" .


...

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titlePhysical Dimension

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Currently Offered Variants 

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Set correct link to the shop page overview table of the product on English and German.

Example for TE0728:

    ENG Page: https://shop.trenz-electronic.de/en/Products/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

    DEU Page: https://shop.trenz-electronic.de/de/Produkte/Trenz-Electronic/TE07XX-Zynq-SoC/TE0728-Zynq-SoC/

For Baseboards or modules, where no overview page is available (and revision number is coded in the direct link) use shop search link, e.g. TE0706:

    ENG Page: https://shop.trenz-electronic.de/en/search?sSearch=TE0706

   DEU Page: https://shop.trenz-electronic.de/de/search?sSearch=TE0706

...

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titleTrenz Electronic Shop Overview

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Trenz shop TEF0003 overview page
English pageGerman page


Revision History

Hardware Revision History

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hiddentrue
idComments

Set correct links to download  arrier, e.g. TE0706 REV02:

  TE0706-02  ->   https://shop.trenz-electronic.de/Download/?path=Trenz_Electronic/Modules_and_Module_Carriers/4x5/4x5_Carriers/TE0706/REV02/Documents

Note:

  • Date format:  YYYY-MM-DD

...

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DateRevisionChangesDocumentation Link
2017-06-27REV01

Initial Release

REV01


Hardware revision number can be found on the PCB board together with the module model number separated by the dash.

Scroll Title
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titleBoard hardware revision number.


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Scroll Only


Document Change History

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  • Note this list must be only updated, if the document is online on public doc!
  • It's semi automatically, so do following

    • Add new row below first

    • Copy "Page Information Macro(date)" Macro-Preview, Metadata Version number, Author Name and description to the empty row. Important Revision number must be the same as the Wiki document revision number Update Metadata = "Page Information Macro (current-version)" Preview+1 and add Author and change description. --> this point is will be deleted on newer pdf export template

    • Metadata is only used of compatibility of older exports
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DateRevisionContributorDescription

Page info
infoTypeModified date
dateFormatyyyy-MM-dd
typeFlat

Page info
infoTypeCurrent version
prefixv.
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Page info
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  • change list

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all

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    • pdf export template

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Scroll Title
anchorTable_RH_DCH
titleDocument change history.

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DateRevisionContributorDescription

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all

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Disclaimer

Include Page
IN:Legal Notices
IN:Legal Notices

...

anchorTable_OBP_CLK
titleOsillators

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orientationportrait
sortDirectionASC
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...

IN0

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Reference input clock.

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XAXB

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-

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GA_PCLK

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FPGA bank 15

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FPGA bank 15

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FPGA bank 15

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FPGA bank 15

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GBTCLK1

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J1E/J6E

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Output

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